On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote: > The LFPS Half Cycle Duration field, as well as the First and Last > LFPS > Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per > Bspec the value programmed must be N_Symbol - 1. The number of > symbols > was programmed directly, making each half cycle one symbol clock too > long. > > Subtract one in the PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION, > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION field macros so the > programmed value matches the zero-based field encoding. > > Bspec: 71632 > Cc: Jouni Högander <[email protected]> > Assisted-by: Claude:claude-opus-4-8 > Signed-off-by: Animesh Manna <[email protected]>
Reviewed-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 8f60b671755a..387edf8df6e9 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -339,11 +339,17 @@ > #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7 > #define > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK,(val)-PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN) > #define > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD,(val)-PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN) > +/* > + * The LFPS half cycle duration fields (including the first and last > half > + * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1. > + * > + * Bspec: 71632 > + */ > #define > PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(20, 16) > -#define > PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK,val) > +#define > PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK,(val)-1) > #define > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(12 > , 8) > -#define > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP > (PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val) > +#define > PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP > (PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1) > #define > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(4, 0) > -#define > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK,val) > +#define > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK,(val)-1) > > #endif /* __INTEL_PSR_REGS_H__ */
