Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] drm/i915: missing clear mask in intel_hdmi_frl_cfg_write() causes register corruption --
commit 0a0fe491d4ed801c5c5d75f8cf1134e058f90bcb Author: Ankit Nautiyal <[email protected]> drm/i915/hdmi: Add helper to write FRL CFG register This commit introduces a helper function, intel_hdmi_frl_cfg_write(), to write FRL CFG register bits. > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c [ ... ] > +void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + enum transcoder cpu_trans = crtc_state->cpu_transcoder; > + u32 val; > + > + if (!crtc_state->frl.enable) > + return; > + > + val = TRANS_HDMI_R_B_SCHED_ENABLE(crtc_state->frl.rsrc_sched_en); > + val |= > TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(crtc_state->frl.active_char_buf_threshold); > + val |= TRANS_HDMI_MIN_BLANK_CHAR(TRANS_HDMI_MIN_BLANK_CHAR_VAL); > + > + intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val); [Severity: Medium] Will this read-modify-write operation accumulate stale bits across multiple modesets? The intel_de_rmw() implementation computes the new register value using (old_val & ~clear) | set. Because 0 is passed as the clear mask here, the new configuration values are simply bitwise OR'd against the old register state. This means multi-bit fields like active_char_buf_threshold could accumulate bits (e.g. changing from 010 to 001 results in 011), and boolean flags like rsrc_sched_en might not transition from true to false once set. Should the clear mask explicitly include TRANS_HDMI_R_B_SCHED_ENABLE_MASK, TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK, and TRANS_HDMI_MIN_BLANK_CHAR_MASK? > +} -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=31
