On Thu, Oct 08, 2026 at 10:53:48PM +0530, Mahadevan P wrote: > dpu_crtc_mode_valid() halves the adjusted mode clock whenever the > hardware has a 3d_mux block, assuming the mode will be driven by two > layer mixers. Modes no wider than MAX_HDISPLAY_SPLIT are driven by a > single mixer, so for those the check permits twice the pixel rate the > datapath can sustain. > > Divide by the mixer count the mode will really be driven by, as reported > by dpu_crtc_num_lm_for_mode(). Split modes still get the halved rate, > single mixer modes are held to what one mixer sustains, and parts > without a 3d_mux divide by one. > > Assisted-by: LLM > Signed-off-by: Mahadevan P <[email protected]> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index 0b51a4c5db57..209b25dbeb6c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -1631,8 +1631,7 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct > drm_crtc *crtc, > adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock, > > dpu_kms->perf.perf_cfg); > > - if (dpu_kms->catalog->caps->has_3d_merge) > - adjusted_mode_clk /= 2; > + adjusted_mode_clk /= dpu_crtc_num_lm_for_mode(dpu_kms, mode);
With the 64-bit division fixed, LGTM. When submitting patches to these drivers please make sure to build for armhf as well as for the arm64. > > /* > * The given mode, adjusted for the perf clock factor, should not exceed > > -- > 2.34.1 > -- With best wishes Dmitry
