Hi Laurent,
On Mon, Oct 19, 2026 at 06:01:16PM +0100, Laurent Pinchart wrote:
>
> This patch series introduces a big penalty in the common case where a
> userspace application consumes the frame with the CPU. There should be
> no cache invalidation in that case.
>
I measured this on my Pi 500+. The cost appears when the DMA-BUF has a
V3D attachment that stays mapped but idle. I compared patch 1 alone with
patches 1-4 on the same v7.3-rc4 base at 640x480 YUYV. For the DMA-BUF
runs, userspace read every frame between DMA_BUF_IOCTL_SYNC READ calls.
Median process CPU time (us/frame), five 1800-frame runs:
patch 1 patches 1-4
DMA-BUF, no DRM import 129.2 130.6
DMA-BUF, idle V3D map 130.0 153.1
MMAP 126.5 125.4
The no-import and MMAP ranges overlapped. The V3D-mapped ranges did not.
Pi 400 reproduced the mapped cost with vivid (+8.7%) and UVC (+7.5%).
The task-clock profile covered only the patched mapped path:
Operation Sample share
DQBUF producer END|WRITE clean 26%
userspace START|READ invalidation 13%
userspace END|READ clean 8%
I tried a CMA experiment that kept the DMA-BUF callbacks but skipped the
read-only END|READ attachment sync. The skip variant saved a median 12.3
us/frame (8.0%) across three alternating same-boot pairs. With private
DMA-BUFs, the full-sync and skip variants both passed 64 byte-checked
V3D read and overwrite cycles after END|READ.
That experiment still performs END|WRITE and START|READ. In a negative
control without END|WRITE, all eight V3D reads returned stale data.
Patch 1 is independent, so I can send it separately.
For patches 2-4: How should vb2 avoid the END|WRITE/START|READ
round trip when userspace consumes the frame with the CPU, while still
publishing the frame if the next consumer is a device?
Thanks,
Karl
