Dear All, This patch series adds DU/DRM support for the 2 Display Units (DUs) interface found on the Renesas RZ/G3E SoC.
RZ/G3E SoC has 2 LCD controller (LCDC0 and LCDC1), both are composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). LCDC0 is connected to LVDS (single or dual channel) and DSI. LCDC1 is connected to LVDS (single ch), DSI, and GPIO (Parallel I/F). Kind regards, Tommaso v8->v9: - Rebased on top of next-20261022 - PATCH 1/10: Step back to v5 -> 2 du model du0 and du1. + added refusal of port3 for others SoCs and adjusted order and ports description. v5: https://lore.kernel.org/all/ca022fdbba5236c36e0cb3095db4c31e8e0cb1b8.1770996493.git.tommaso.merciai...@bp.renesas.com/ - PATCH 3/10: Dropped the vsp_pipe bounds check in rzg2l_du_crtc_create() and the now unused num_planes field, aligning with rcar_du_crtc_create(). - PATCH 9/10: Added newly architetture support creating an ad hoc component driver for RZ/G3E display subsystem that embed the 2 du instances into single drm device. - PATCH 10/10: Split du into du0 and du1 node and added newly display_subsystem node. - Improved cover letter. v7->v8: - Rebased on top of next-20260827 + [1]. - Improved cover letter. - Modelled using ports/port instead of port/ep. - PATCH 01/9: Add RZ/G3E support on top of [1] using R-Car like architecture, improved commit msg and commit body. - PATCH 08/9: Use R-Car like architecture for RZ/G3E and added mode_clock_min, mode_clock_max for parallel output, improved commit msg and commit body. v6->v7: - Rebased on top of next-20260605 - Splitted the original series into smaller chunks for easy review and easy merging. The original series is available here: http://lore.kernel.org/all/[email protected]/ - PATCH 01/13: Collected LPinchart tag. Removed wrong fixes tag. - PATCH 02/13: Rebased on top of [1]. Use single DRM device aggregating both DU instances (1 DU dt node), modelling single port for each DU0, DU1 and multiple endpoints for outputs. - PATCH 12/13: Removed feature flag usage, rebased on top of T2H/N2H LCDC series [1] Reworked commit body as now outputs routing is based on endpoint id instead of port number. Fixed rzg2l_du_r9a09g047_info instead of rzg2l_du_r9a09g047_du_info. Added bump of RZG2L_DU_MAX_CRTCS and RZG2L_DU_MAX_VSPS to 2. v5->v6: - Rebased on top of next-20260406 - PATCH 1: Fixed rzv2h_cpg_plldsi_smux_clk_register() removed u8 width, mask variables and replaced with direct use of smux.width and clk_div_mask(smux.width). - PATCH 9: New patch. - PATCH 10: Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and explicitly disable port@2 and port@3 for existing SoCs that do not expose them. Reworked ports numbering + improved/fixed ports descriptions in the bindings documentation. Improved commit body. - PATCH 15: Aligned ports numbering with the bindings changes. - PATCH 20: Update ports numbering accordingly to the latest DT bindings. v4->v5: - Rebased on top of next-20260211 - PATCH 9: Dropped renesas,id property. - PATCH 10: Collected tag. - PATCH 14: Fixed RG2L_DU_FEATURE_SMUX2_DSI_CLK to RZG2L_DU_FEATURE_SMUX2_DSI_CLK Added features field documentation. - PATCH 19: Rename du0_out_dsi0 into du0_out_dsi. Rename du1_out_dsi0 into du1_out_dsi. Drop renesas,id entry from DU nodes. - PATCH 20: Use DU0 -> DSI instead of DU1 -> DSI. v3->v4: - Rebased on top of next-20260130 - PATCH 1: Fixed build error: https://lore.kernel.org/oe-kbuild-all/[email protected]/ v2->v3: - PATCH 1: Added missing defines for duty num/den. v1->v2: - Rebased on top of next-20260129. - PATCH 1: Added rzv2h_cpg_plldsi_smux_{get,set}_duty_cycle clock operations to allow the DRM driver to query and configure the appropriate clock path based on the required output duty cycle. Updated commit message accordingly. - PATCH 2-5: Collected tags. - PATCH 6: Moved clk_ids to match enum order. - PATCH 7: Collected GUytterhoeven tag. Fixed "dsi_0_vclk2" position to match order. - PATCH 8: Collected GUytterhoeven tag. - PATCH 9: Use single compatible string instead of multiple compatible strings for the two DU instances, leveraging a 'renesas,id' property to differentiate between DU0 and DU1. Updated commit message. - PATCH 10: Removed oneOf from clocks property, which is not sufficient to differentiate between RZ/G3E, RZ/V2H(P) and RZ/G2L. Use the already existing vclk instead of vclk1 for RZ/G3E DSI bindings. Updated allOf. - PATCH 14: Instead of using clk-provider API to select the right parent clock, just set the correct duty cycle based on the output. Updated commit message accordingly. - PATCH 15-16: Collected tags. - PATCH 17: Squashed fcpvd0 and fcpvd1 patches into a single patch. Collected tags. - PATCH 18: Squashed vspd0 and vspd1 patches into a single patch. Collected tags. - PATCH 19: Reworked DU nodes to use single compatible. Use vclk instead of vclk1 for DSI Node and set to the right position. - PATCH 20: Fixed: dsi, du and adv7535 are part of the R9A09G047E57 SMARC SoM board then add entries in the rzg3e-smarc-som.dtsi instead of using the r9a09g047e57-smarc-du1-adv7535.dtsi. Tommaso Merciai (10): dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC dt-bindings: display: Document Renesas RZ/G3E display subsystem drm: renesas: rz-du: vsp: Keep the planes in the VSP drm: renesas: rz-du: Reference the DRM device by pointer drm: renesas: rz-du: Count all registered encoders for the possible clones drm: renesas: rz-du: Split the mode setting initialization drm: renesas: rz-du: Make the CRTC index relative to the DRM device drm: renesas: rz-du: Share the encoder of an output driven by several DUs drm: renesas: rz-du: Add RZ/G3E (R9A09G047) DU support arm64: dts: renesas: r9a09g047: Add DU{0,1} and display subsystem nodes .../renesas,r9a09g047-display-subsystem.yaml | 44 ++++ .../bindings/display/renesas,rzg2l-du.yaml | 28 ++- MAINTAINERS | 1 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 80 ++++++ drivers/gpu/drm/renesas/rz-du/Makefile | 1 + drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 6 +- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 108 ++++++-- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 21 +- .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 23 +- .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.h | 1 + drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 60 +++-- drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.h | 3 + .../drm/renesas/rz-du/rzg2l_du_subsystem.c | 231 ++++++++++++++++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c | 23 +- drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h | 10 +- 15 files changed, 564 insertions(+), 76 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/renesas,r9a09g047-display-subsystem.yaml create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_subsystem.c -- 2.54.0
