Add DU{0,1} and the display subsystem nodes to RZ/G3E SoC DTSI.
Signed-off-by: Tommaso Merciai <[email protected]>
---
v8->v9:
- Split du into du0 and du1 node and added newly display_subsystem node.
v7->v8
- New patch
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 80 ++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 737bf1c60451..0d03121a37e1 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -153,6 +153,12 @@ opp-19687500 {
};
};
+ display_subsystem: display-subsystem {
+ compatible = "renesas,r9a09g047-display-subsystem";
+ ports = <&du0_ports>, <&du1_ports>;
+ status = "disabled";
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -2239,6 +2245,80 @@ csi2cru: endpoint@0 {
};
};
+ du0: display@16460000 {
+ compatible = "renesas,r9a09g047-du";
+ reg = <0 0x16460000 0 0x10000>;
+ interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,vsps = <&vspd0 0>;
+ status = "disabled";
+
+ du0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du0_out_dsi: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ du0_out_lvds0: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ du0_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
+
+ du1: display@16490000 {
+ compatible = "renesas,r9a09g047-du";
+ reg = <0 0x16490000 0 0x10000>;
+ interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0x1a8>,
+ <&cpg CPG_MOD 0x1a9>,
+ <&cpg CPG_MOD 0x1aa>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x11e>;
+ renesas,vsps = <&vspd1 0>;
+ status = "disabled";
+
+ du1_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du1_out_dsi: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du1_out_rgb: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ du1_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
+
fcpvd0: fcp@16470000 {
compatible = "renesas,r9a09g047-fcpvd",
"renesas,fcpv";
--
2.54.0
