Issue a AUX write transaction to DPCD DP_TOTAL_LTTPR_CNT (0xf000a) with total number of LTTPR before link training.
v2: Cosmetic changes. [Suraj] v3: - Use same encoding format for lttpr_count. [Jouni] - Avoid reading alpm_ctl2 register. [Jouni] v4: - Program DP_TOTAL_LTTPR_CNT only for DP, not eDP. [Jouni, sashiko] - Drop redundant lttpr_count check. [Jouni, sashiko] - Check drm_dp_lttpr_count() return value before programming ALPM_CTL2. [Jouni, sashiko] - Fix LTTPR revision check to match the comment. [sashiko] - Use drm_dp_dpcd_write_byte(). [Jani] Cc: Jouni Högander <[email protected]> Cc: Jani Nikula <[email protected]> Signed-off-by: Animesh Manna <[email protected]> --- drivers/gpu/drm/i915/display/intel_alpm.c | 10 +++++++++- .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index f3c0884989ce..831dfa5e677b 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -687,7 +687,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - u32 alpm_ctl; + u32 alpm_ctl, alpm_ctl2; + int lttpr_count; if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)) @@ -725,6 +726,13 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines); + lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); + if (lttpr_count < 0) + lttpr_count = 0; + + alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count); + + intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2); intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl); mutex_unlock(&intel_dp->alpm.lock); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index ac1aff6edf05..0dbc6174c402 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -2271,6 +2271,24 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, return passed; } +static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp) +{ + u8 val; + + /* + * Program only for DP and return if LTTPR revision is less than 0x20 + * where 0:3 represents minor rev and 4:7 represent major rev + */ + if (intel_dp_is_edp(intel_dp) || + intel_dp->lttpr_common_caps[0] < 0x20) + return; + + val = intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; + if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, val) < 0) + lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to write total LTTPR count\n"); +} + /** * intel_dp_start_link_train - start link training * @state: Atomic state @@ -2310,6 +2328,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, intel_dp_prepare_link_train(intel_dp, crtc_state); + intel_dp_update_lttpr_count(intel_dp); + if (intel_dp_is_uhbr(crtc_state)) passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); else -- 2.43.0
