The AUX_LESS_WAKE_TIME bitfield in ALPM_CTL is widened from 6 bits to 8 bits starting from xe3lpd (display version 35). Add the register mask and field macro for the wider bitfield and program the wake time using the appropriate macro based on the display version. Also use the wider limit when validating the computed wake lines and for the safest params fallback.
v2: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd. [Suraj] v3: Separate out AUX_LESS_WAKE_TIME bitfield change into its own patch. [Jouni] v4: Use the wider bitfield limit in aux-less wake time computation and safest params. [Jouni, sashiko] Bspec: 71477 Cc: Jouni Högander <[email protected]> Signed-off-by: Animesh Manna <[email protected]> --- drivers/gpu/drm/i915/display/intel_alpm.c | 20 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index b9e31c29ab96..0083752d94f0 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -204,6 +204,12 @@ static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp, establishment_period, 1000); } +static int get_aux_less_wake_lines_max(struct intel_display *display) +{ + return DISPLAY_VER(display) >= 35 ? ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD : + ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; +} + static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) @@ -220,14 +226,14 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state); - if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK || + if (aux_less_wake_lines > get_aux_less_wake_lines_max(display) || silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK || lfps_half_cycle < 1 || lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK + 1) return false; if (display->params.psr_safest_params) - aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; + aux_less_wake_lines = get_aux_less_wake_lines_max(display); crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines; crtc_state->alpm_state.silence_period_sym_clocks = silence_period; @@ -617,10 +623,16 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, * check panel support at this point. */ if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { + int wake_lines = crtc_state->alpm_state.aux_less_wake_lines; + alpm_ctl = ALPM_CTL_ALPM_ENABLE | ALPM_CTL_ALPM_AUX_LESS_ENABLE | - ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS | - ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines); + ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; + + if (DISPLAY_VER(display) < 35) + alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME(wake_lines); + else + alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(wake_lines); if (intel_dp->as_sdp_supported) intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 78a05387eab5..124aa74e1dbb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -301,7 +301,9 @@ #define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 #define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) #define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) +#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD REG_GENMASK(7, 0) #define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) +#define ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD, val) #define _ALPM_CTL2_A 0x60954 #define ALPM_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A) -- 2.43.0
