The snapshot code will need more control, setting additional bitfields. Rather than add a list of additional args, add a helper to acquire the aperture which directly takes a reg value.
Signed-off-by: Rob Clark <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 21 +++++++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index fb000b79fe2f..2a2ddba6761f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -348,6 +348,7 @@ void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); void a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int a6xx_zap_shader_init(struct msm_gpu *gpu); +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags); void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags); void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags); void a8xx_aperture_clear(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index a14379e26fbe..a0983e2ee641 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -16,13 +16,10 @@ #define GPU_PAS_ID 13 -static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, u32 val) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - u32 val; - - val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); if (a6xx_gpu->cached_aperture == val) return; @@ -32,14 +29,20 @@ static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, a6xx_gpu->cached_aperture = val; } -void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); - a8xx_aperture_slice_set(gpu, pipe, 0); + a8xx_aperture_slice_set(gpu, val); + +} + +void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +{ + a8xx_aperture_acquire_raw(gpu, A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe), flags); } void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) @@ -74,8 +77,10 @@ static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 unsigned long flags; u32 val; - spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags); - a8xx_aperture_slice_set(gpu, pipe, slice); + a8xx_aperture_acquire_raw(gpu, + A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | + A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice), + &flags); val = gpu_read(gpu, offset); spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); -- 2.56.0
