If there are not enough global CP_PROTECT_GLOBAL regs, we can use CP_PROTECT_PIPE regs for the extra spans. We just need to configure them the same on all pipes.
Signed-off-by: Rob Clark <[email protected]> --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index a6146372cf7e..1f8dd688b967 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -258,12 +258,21 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) a8xx_aperture_clear(gpu); - for (i = 0; i < protect->count; i++) { + for (i = 0; i < min(64, protect->count); i++) { /* Intentionally skip writing to some registers */ - if (protect->regs[i]) { - gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); - final_cfg = protect->regs[i]; - } + if (!protect->regs[i]) + continue; + gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); + final_cfg = protect->regs[i]; + } + + for (; i < protect->count; i++) { + /* Intentionally skip writing to some registers */ + if (!protect->regs[i]) + continue; + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + final_cfg = protect->regs[i]; } /* -- 2.56.0
