Re: [PATCH v5 09/15] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch

[Daniel Stone]

Hi,

On Tue, 13 Oct 2026 at 23:51, Cristian Ciocaltea
<cristian.ciocal...@collabora.com> wrote:
> +                       if (!vp->dclk_src)
> +                               vp->dclk_src = clk_get_parent(vp->dclk);

Why not do this at init, where we setup the rest of our clock tree?

The rest is:
Reviewed-by: Daniel Stone <dani...@collabora.com>

Cheers,
Daniel