I seem to have bought a recent release of the Radeon 8500 that the DRI
code doesn't recognize. So, I've been trying to build the DRI code to
try to learn a bit about what's going on and maybe get X working with my
card.
One thing that I've run across, and possibly Karl Meisterheim as well
(from an earlier post in the dri-user list) is the compiler error:
gcc: cannot specify -o with -c or -S and multiple compilations
For me, it turned out that when I uncommented the ProjectRoot variable
in the host.def file, I left a trailing blank at the end of the path.
This causes a space between the include path, and the trailing backslash
that's added in the makefiles. For us folk who are green to the
purpose of the ProjectRoot variable, this can be difficult to catch.
Would it be possible to put a comment above the ProjectRoot variable
warning not to leave a trailing blank?
I've read in various places that the code is a work in progress so when
it's checked out, not to expect it to build or work correctly. This
does seem to be the case, so I'd like to get a release of the code
that's stable.
How do I go about pulling a a specific version of the CVS tree that will
compile cleanly and run ? What version of the code fits this bill?
About my card, in the hope that this will show the owners of the radeon
probing code other variations that are showing in the radeons, here's
some output from XFree86.log, and the output from lspci. Let me know
if you need anything else.
(II) Bus 1: bridge is at (0:1:0), (0,1,1), BCTRL: 0x0c (VGA_EN is set)
(II) Bus 1 I/O range:
[0] -1 0x0000c000 - 0x0000c0ff (0x100) IX[B]
[1] -1 0x0000c400 - 0x0000c4ff (0x100) IX[B]
[2] -1 0x0000c800 - 0x0000c8ff (0x100) IX[B]
[3] -1 0x0000cc00 - 0x0000ccff (0x100) IX[B]
(II) Bus 1 non-prefetchable memory range:
[0] -1 0xec000000 - 0xedffffff (0x2000000) MX[B]
(II) Bus 1 prefetchable memory range:
[0] -1 0xe0000000 - 0xe7ffffff (0x8000000) MX[B]
(II) Bus -1: bridge is at (0:17:0), (0,-1,0), BCTRL: 0x08 (VGA_EN is set)
(II) Bus -1 I/O range:
(II) Bus -1 non-prefetchable memory range:
(II) Bus -1 prefetchable memory range:
(--) PCI:*(1:0:0) ATI unknown chipset (0x514c) rev 0, Mem @
0xe0000000/27, 0xed000000/16, I/O @ 0xc000/8
here's the output from lspci -vv:
01:00.0 VGA compatible controller: ATI Technologies Inc: Unknown device
514c (prog-if 00 [VGA])
Subsystem: ATI Technologies Inc: Unknown device 013a
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping+ SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: Memory at e0000000 (32-bit, prefetchable) [size=128M]
Region 1: I/O ports at c000 [size=256]
Region 2: Memory at ed000000 (32-bit, non-prefetchable) [size=64K]
Expansion ROM at <unassigned> [disabled] [size=128K]
Capabilities: [58] AGP version 2.0
Status: RQ=47 SBA+ 64bit- FW+ Rate=x1,x2
Command: RQ=0 SBA+ AGP- 64bit- FW- Rate=<none>
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
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