Ian, now that you've merged in the software support for combine3 from the
Mesa trunk, I'm trying to get it working in hardware on R100 with texmem
(impatient as I am ;) ). I don't have Radeon docs, so I'm guessing about
the registers. I'm attaching a patch of what I've got. My assumptions
are that RADEON_BLEND_CTL_[ADD,ADDSIGNED,SUBTRACT] will do the
corresponding MODULATE_[ADD,ADDSIGNED,SUBTRACT] with three args. Also,
I'm assuming I can use RADEON_[COLOR,ALPHA]_ARG_A_ZERO or-ed with
_COMP_ARG_A to get GL_ONE.
Does this look right? Ian, you mentioned seeing problems with SUBTRACT,
and in an older message you were wondering about the difference between
how r100 and r200 handle PREVIOUS. Two questions: Did you come to any
conclusions on either of those questions? and what are you using to test
this? I was thinking of trying to add support to the glean texcombine
test, but I wanted to see if you had something already.
Also, should I go ahead and commit my revised texmem patch?
--
Leif Delgass
http://www.retinalburn.net
Index: radeon_context.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v
retrieving revision 1.20.2.7
diff -u -r1.20.2.7 radeon_context.c
--- radeon_context.c 5 Dec 2002 15:26:34 -0000 1.20.2.7
+++ radeon_context.c 5 Feb 2003 19:19:51 -0000
@@ -137,6 +137,7 @@
"GL_EXT_texture_env_dot3",
"GL_EXT_texture_filter_anisotropic",
"GL_EXT_texture_lod_bias",
+ "GL_ATI_texture_env_combine3",
"GL_ATI_texture_mirror_once",
"GL_IBM_texture_mirrored_repeat",
"GL_NV_blend_square",
Index: radeon_texstate.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c,v
retrieving revision 1.8.2.5
diff -u -r1.8.2.5 radeon_texstate.c
--- radeon_texstate.c 5 Dec 2002 15:26:43 -0000 1.8.2.5
+++ radeon_texstate.c 5 Feb 2003 19:19:52 -0000
@@ -119,7 +119,7 @@
t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter;
}
else {
- _mesa_problem(NULL, "unexpected texture format in radeonTexImage2D");
+ _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__);
return;
}
@@ -198,7 +198,6 @@
assert(t->image[0][i].x == 0
|| (size < BLIT_WIDTH_BYTES && t->image[0][i].height == 1));
#endif
- curOffset += size;
if (0)
fprintf(stderr,
@@ -206,6 +205,9 @@
i, texImage->Width, texImage->Height,
t->image[0][i].x, t->image[0][i].y,
t->image[0][i].width, t->image[0][i].height, size, curOffset);
+
+ curOffset += size;
+
}
/* Align the total size of texture memory block.
@@ -670,6 +672,22 @@
RADEON_COLOR_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
};
+static GLuint radeon_zero_color[] =
+{
+ RADEON_COLOR_ARG_A_ZERO,
+ RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
+ RADEON_COLOR_ARG_A_ZERO,
+ RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A
+};
+
+static GLuint radeon_one_color[] =
+{
+ RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
+ RADEON_COLOR_ARG_A_ZERO,
+ RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
+ RADEON_COLOR_ARG_A_ZERO
+};
+
/* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
*/
static GLuint radeon_texture_alpha[][RADEON_MAX_TEXTURE_UNITS] =
@@ -704,6 +722,17 @@
RADEON_ALPHA_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
};
+static GLuint radeon_zero_alpha[] =
+{
+ RADEON_ALPHA_ARG_A_ZERO,
+ RADEON_ALPHA_ARG_A_ZERO | RADEON_COMP_ARG_A
+};
+
+static GLuint radeon_one_alpha[] =
+{
+ RADEON_ALPHA_ARG_A_ZERO | RADEON_COMP_ARG_A,
+ RADEON_ALPHA_ARG_A_ZERO
+};
/* Extract the arg from slot A, shift it into the correct argument slot
* and set the corresponding complement bit.
@@ -900,6 +929,9 @@
numColorArgs = 2;
break;
case GL_INTERPOLATE:
+ case GL_MODULATE_ADD_ATI:
+ case GL_MODULATE_SIGNED_ADD_ATI:
+ case GL_MODULATE_SUBTRACT_ATI:
numColorArgs = 3;
break;
default:
@@ -917,6 +949,9 @@
numAlphaArgs = 2;
break;
case GL_INTERPOLATE:
+ case GL_MODULATE_ADD_ATI:
+ case GL_MODULATE_SIGNED_ADD_ATI:
+ case GL_MODULATE_SUBTRACT_ATI:
numAlphaArgs = 3;
break;
default:
@@ -943,6 +978,12 @@
case GL_PREVIOUS:
color_arg[i] = radeon_previous_color[op];
break;
+ case GL_ZERO:
+ color_arg[i] = radeon_zero_color[op];
+ break;
+ case GL_ONE:
+ color_arg[i] = radeon_one_color[op];
+ break;
default:
return GL_FALSE;
}
@@ -965,6 +1006,12 @@
case GL_PREVIOUS:
alpha_arg[i] = radeon_previous_alpha[op];
break;
+ case GL_ZERO:
+ color_arg[i] = radeon_zero_alpha[op];
+ break;
+ case GL_ONE:
+ color_arg[i] = radeon_one_alpha[op];
+ break;
default:
return GL_FALSE;
}
@@ -1036,6 +1083,28 @@
RADEON_COLOR_ARG( 0, A );
RADEON_COLOR_ARG( 1, B );
break;
+
+ case GL_MODULATE_ADD_ATI:
+ color_combine = (RADEON_BLEND_CTL_ADD |
+ RADEON_CLAMP_TX);
+ RADEON_COLOR_ARG( 0, A );
+ RADEON_COLOR_ARG( 1, C );
+ RADEON_COLOR_ARG( 2, B );
+ break;
+ case GL_MODULATE_SIGNED_ADD_ATI:
+ color_combine = (RADEON_BLEND_CTL_ADDSIGNED |
+ RADEON_CLAMP_TX);
+ RADEON_COLOR_ARG( 0, A );
+ RADEON_COLOR_ARG( 1, C );
+ RADEON_COLOR_ARG( 2, B );
+ break;
+ case GL_MODULATE_SUBTRACT_ATI:
+ color_combine = (RADEON_BLEND_CTL_SUBTRACT |
+ RADEON_CLAMP_TX);
+ RADEON_COLOR_ARG( 0, A );
+ RADEON_COLOR_ARG( 1, C );
+ RADEON_COLOR_ARG( 2, B );
+ break;
default:
return GL_FALSE;
}
@@ -1085,6 +1154,28 @@
RADEON_ALPHA_ARG( 0, B );
RADEON_ALPHA_ARG( 1, A );
RADEON_ALPHA_ARG( 2, C );
+ break;
+
+ case GL_MODULATE_ADD_ATI:
+ alpha_combine = (RADEON_BLEND_CTL_ADD |
+ RADEON_CLAMP_TX);
+ RADEON_ALPHA_ARG( 0, A );
+ RADEON_ALPHA_ARG( 1, C );
+ RADEON_ALPHA_ARG( 2, B );
+ break;
+ case GL_MODULATE_SIGNED_ADD_ATI:
+ alpha_combine = (RADEON_BLEND_CTL_ADDSIGNED |
+ RADEON_CLAMP_TX);
+ RADEON_ALPHA_ARG( 0, A );
+ RADEON_ALPHA_ARG( 1, C );
+ RADEON_ALPHA_ARG( 2, B );
+ break;
+ case GL_MODULATE_SUBTRACT_ATI:
+ alpha_combine = (RADEON_BLEND_CTL_SUBTRACT |
+ RADEON_CLAMP_TX);
+ RADEON_ALPHA_ARG( 0, A );
+ RADEON_ALPHA_ARG( 1, C );
+ RADEON_ALPHA_ARG( 2, B );
break;
default:
return GL_FALSE;
