On Mon, 3 Mar 2003 10:48:54 -0800 Philip Brown <[EMAIL PROTECTED]> wrote: > > But anyway, sounds like I can NOP it out, I guess.
You may be able to NOP it if your platform does not require it. I know the Alpha uses memory barriers. I think PPC may use them too. Here's a bit from the Alpha Architecture Handbook on the Alpha's memory barrier instruction: "Description: The use of the Memory Barrier (MB) instruction is required only in multiprocessor systems. In the absence of an MB instruction, loads and stores to different physical locations are allowed to complete out of order on the issuing processor as observed by other processors. The MB instruction allows memory accesses to be serialized on the issuing processor as observed by other processors. See Chapter 5 for details on using the MB instruction to serialize these accesses. Chapter 5 also details coordinating memory accesses across processors. Note that MB ensures serialization only; it does not necessarily accelerate the progress of memory operations." While the handbook indicates it's only required on multprocessor systems, they are used on single processor systems to ensure write(s) are committed before the next read or re-read. Alan ------------------------------------------------------- This SF.net email is sponsored by: Etnus, makers of TotalView, The debugger for complex code. Debugging C/C++ programs can leave you feeling lost and disoriented. TotalView can help you find your way. Available on major UNIX and Linux platforms. Try it free. www.etnus.com _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
