Jon Smirl writes: > > It works, but it's illegal. That means that the CPU might well speculate > > a load from one of these pages in kernel-land just because it happens to > > be next to a page where you are iterating an array, and may then bring a > > bit in the cache from that page. > > That shouldn't matter the page brought in would be for a speculative > read and never accessed. It should just fall out of the cache and not > be written back. There is only one cachable mapping. In this model > writes are always followed by a flush before telling the GPU to access > the memory that has just been written.
That would be fine, but it would mean making sure that every time any code in the DRI, DRM or X server writes to the AGP memory, it does the flush as well. Sounds like a maintenance nightmare to me... Paul. ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_id=6595&alloc_id=14396&op=click -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
