On Wed, 16 Mar 2005, Michel [ISO-8859-1] Dänzer wrote:
Disclaimer: I don't pretend to understand 100% how all this stuff works either, but I think my understanding has improved a little recently. :)
Michel, I think we are misunderstanding each other.
I am not talking about synchronization of drawing operations, I am talking about hardware limitations.
I am quite certain, that, at least on mach64 hardware, an attempt to access framebuffer by CPU while the GUI engine is active will result in a hard lockup.
The same goes for other rules I quoted.
These rules were never spelled out in any Radeon documentation I had, so I assumed they carried over, as that documentation had sections removed.
The lockup when GUI is active and your read GUI MMIO register is not due to synchonization alone.
However, some registers can be accessed at any time - most obviously the STATUS registers which tell us when the GUI is active.
If you (as a priveleged person) could make certain whether this limitation exists or not, it would be really great :)
The issue of hard lockups with CPU reads from card apertures is one of the few features of ATI hardware I am truly unhappy about, (the other, of course, is a relatively closed documentation, albeit the situation is clearly better than some other manufacturers)
best
Vladimir Dergachev
On Tue, 2005-03-15 at 20:07 -0500, Vladimir Dergachev wrote:
On Tue, 15 Mar 2005, Vladimir Dergachev wrote:
My understanding was that for MMIO-only access:
* Check that FIFO is not full before writing
This one is obvious (for FIFO'd registers). :)
* Check that GUI engine is idle before accessing framebuffer
Technically you'd only have to make sure that the engine isn't operating on the same 'area' as the CPU I think, but waiting for idle is usually a good way to be on the safe side here.
* Check that FIFO is empty before reading a register
Forgot the forth one: some registers bypass the FIFO, so WaitForIdle for them is not necessary.
The FIFO doesn't apply to reads. It only applies to some register writes, basically the ones where queueing makes sense, i.e. mostly to acceleration related registers.
I have yet to see a 'wait for idle' rule for register access anywhere.
-- Earthling Michel Dänzer | Debian (powerpc), X and DRI developer Libre software enthusiast | http://svcs.affero.net/rm.php?r=daenzer
