--- Comment #8 from Oliver McFadden <[EMAIL PROTECTED]>  2008-03-27 22:23:03 
PST ---
I would rather *NOT* see this patch committed to Mesa, as it really just hides
the issue: we're doing something wrong, which should be fixed.

This must be a sync problem because more aggressive flushing can solve the
problem, though it's not the correct solution.

A discussion on IRC between MrCooper and glisse mentioned the NQWAIT_UNTIL
(0xe50) register. I've seen the blob write this register in Revenge dumps, but
it's never used by our drivers.

I wouldn't mind getting some comments from AMD describing the precisely correct
way to flush and synchronize the ASIC. We're obviously missing something. I
guess tcore might provide this information once it's released...

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