Steven Stallion wrote:
> All,
>
> As a part of emancipation I am working on scratch writing a PCI NE2000
> driver (ne); I had a general question about efficiently handling DMA on
> the DP8390 chipsets:
>
> From the specification, it appears that DMA can be configured as a
> single 32-bit channel with access to a single 64k ring. I am not sure
> how this stacks up to other chipsets, but this ring is divided between
> rx and tx (at the discretion of the driver).
>
> So my question is this: Does it make sense to partition the buffer such
> that enough space is allocated for sending a single packet (i.e. 256 * 6
> perhaps) at the end of the ring, and rest used for reception?
>
> Send packet commands must be issued in serial, but I am concerned that
> using a single descriptor could create a bottleneck (even for 10mbps).
> Would it be better to essentially double buffer transmits using 2
> descriptors?
>
> Thoughts?
>
>
In a word: Yes.
I don't know enough about the chipset., but I'd probably allocate more
than 2, even, since you might be passed down a packet chain and don't
want to have to putbq() the packets (or have GLDv3 do so for you).
Although, pcnet isn't going to be fast in any case. :-) You have room
for 40 1600 byte frames (not including descriptor overhead) -- I'd
configure 16 frames in each direction -- experience with other NIC
drivers has shown that such a configuration works well. If that's too
many, maybe do 16 rx and 8 tx.
-- Garrett
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