The relevant sequences consist of two I/O memory writes. The second write
depends on the first one. mmiowb() was inserted to make sure that no other
thread inserts a "first write" before the current one finished its second.
As a mutex protects this critical sequence, mmiowb() is unnecessary.
Signed-off-by: Eli Billauer <eli.billa...@gmail.com>
---
drivers/staging/xillybus/xillybus_core.c | 4 ----
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/xillybus/xillybus_core.c
b/drivers/staging/xillybus/xillybus_core.c
index 93a3c61..138c069 100644
--- a/drivers/staging/xillybus/xillybus_core.c
+++ b/drivers/staging/xillybus/xillybus_core.c
@@ -908,8 +908,6 @@ static ssize_t xillybus_read(struct file *filp, char __user
*userbuf,
channel->endpoint->registers +
fpga_buf_ctrl_reg);
- mmiowb(); /* Just to appear safe */
-
mutex_unlock(&channel->endpoint->
register_mutex);
}
@@ -1118,7 +1116,6 @@ static int xillybus_myflush(struct xilly_channel
*channel, long timeout)
(2 << 24) | /* Opcode 2, submit buffer */
(bufidx << 12),
channel->endpoint->registers + fpga_buf_ctrl_reg);
- mmiowb(); /* Just to appear safe */
mutex_unlock(&channel->endpoint->register_mutex);
} else if (bufidx == 0)
@@ -1369,7 +1366,6 @@ static ssize_t xillybus_write(struct file *filp, const
char __user *userbuf,
(bufidx << 12),
channel->endpoint->registers +
fpga_buf_ctrl_reg);
- mmiowb(); /* Just to appear safe */
mutex_unlock(&channel->endpoint->
register_mutex);
--
1.7.2.3
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