Branch: refs/heads/master
Home: https://github.com/dyninst/dyninst
Commit: d9426a14d4cbaad486193fb8baa78afdf62d736c
https://github.com/dyninst/dyninst/commit/d9426a14d4cbaad486193fb8baa78afdf62d736c
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-21 (Tue, 21 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Clean up and improve documentation of x86_32 registers (#1629)
* Improve comments for register lengths
* Separate MMX/3DNow! and x87 register lengths and categories
The MMX* registers are only the lower 64 bits of the st* ones.
* Improve comments for EFLAGS fields
* Add conversion to ROSE register for FLAGC
FLAGC is the lower bit of the I/O Permission Level field in EFIELD.
* Add conversion to ROSE register for FLAGD
FLAGC is the upper bit of the I/O Permission Level field in EFIELD.
* Add conversion to ROSE register for Nested Task flag
* Add conversion to ROSE register for Resume Flag
* Add missing Virtual-8086 mode (VM) EFLAGS field
* Add missing Alignment Check/Access Control (AC) EFLAGS field
* Add missing Virtual Interrupt Flag (VIF) EFLAGS field
* Add missing Virtual Interrupt Pending (VIP) EFLAGS field
* Add missing ID Flag (ID) EFLAGS field
* Remove registers xmm8-xmm31 and aliases
These registers are only available in 64-bit mode.
From Intel(r) 64 and IA-32 Architectures Software Developer’s Manual
June 2021:
11.2.1 SSE2 in 64-Bit Mode and Compatibility Mode
In compatibility mode, SSE2 extensions function like they do in
protected mode. In 64-bit mode, eight additional XMM registers are
accessible. Registers XMM8-XMM15 are accessed by using REX prefixes.
14.1.1 256-Bit Wide SIMD Register Support
Intel AVX introduces support for 256-bit wide SIMD registers
(YMM0-YMM7 in operating modes that are 32-bit or less, YMM0-YMM15 in
64-bit mode).
15.1.2 32 SIMD Register Support
Intel AVX-512 instructions also support 32 SIMD registers in 64-bit
mode (XMM0-XMM31, YMM0-YMM31 and ZMM0-ZMM31). The number of available
vector registers in 32-bit mode is still 8.
* Fix avx-512 opmask size.
It's 64 bits, not 128.
From Intel(R) 64 and IA-32 Architectures Software Developer’s Manual
June 2021
15.6.1 OPMASK Register to Predicate Vector Data Processing
The opmask is a set of eight architectural registers of size
MAX_KL (64-bit).
* Rename OCT to XMMS
This makes it consistent with the names used for the other vector
extensions.
* Use symbolic names for the segment register base IDs
* Add missing ROSE category conversions
* Add missing ROSE subrange conversions
* Preserve register number in getBaseRegister
* Clear whole subrange byte for GPRs in getBaseRegister
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