Hey thanks for useful reply!
I have wrote a small driver for PF and VF. I am using ioctl to send data.
Problem is both PF and VF are using the same queues to send data though I
have set the register as bellow
HAL_WRITE_REG(ndev, PFDTXGSWC, PFDTXGSWC_VT_LBEN);
HAL_READ_REG(ndev, VT_CTL, &dwval);
dwval |= VT_CTL_VT_ENABLE;
dwval &= ~VT_CTL_POOL_MASK;
dwval |= vf_count << VT_CTL_POOL_SHIFT;
dwval |= VT_CTL_REPLEN;
//dwval |= 0 << VT_CTL_POOL_SHIFT;
HAL_WRITE_REG(ndev, VT_CTL, dwval);
HAL_READ_REG(ndev, IXGBE_GPIE, &dwval);
dwval &= ~ 0x0000C000;
dwval |= IXGBE_GPIE_VTMODE_16;
HAL_WRITE_REG(ndev, IXGBE_GPIE, dwval);
HAL_WRITE_REG(ndev, VFRE(0), 0xFFFFFFFF);
HAL_WRITE_REG(ndev, VFRE(1), 0xFFFFFFFF);
HAL_WRITE_REG(ndev, VFTE(0), 0xFFFFFFFF);
HAL_WRITE_REG(ndev, VFTE(1), 0xFFFFFFFF);
dwval = 0;
HAL_READ_REG(ndev, GCR_EXT, &dwval);
dwval |= GCR_EXT_VT_MODE_16;
HAL_WRITE_REG(ndev, GCR_EXT, dwval);
I only can use first VF to send data and if i print the head and tail
descriptor from both pf an vf
they both are same. What I am missing.
On Thu, Sep 12, 2013 at 9:22 PM, Greg Rose <[email protected]> wrote:
> On Thu, 12 Sep 2013 19:25:56 +0530
> nirmoy das <[email protected]> wrote:
>
> > Hey,
> >
> > I am trying to write my own driver for intel 82599. After enabling
> > 63 VF using pci_enable_sriov(), How rx/tx queue distribution happen
> > amoung PF and VF?
> >
> > Is PF is using first pool of queues like in 16 Mode PF gets 0-7
> > queues?
> >
>
> The queue indexing per pool assignments are described in the 82599
> 10Gb Ethernet Controller Datasheet in the Rx Queues Assignment
> section. That is section 7.1.2 of the Inline Functions section.
>
> - Greg
>
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