As result of recent re-design of the MSI/MSI-X interrupts enabling
pattern this driver has to be updated to use the new technique to
obtain a optimal number of MSI/MSI-X interrupts required.

Signed-off-by: Alexander Gordeev <agord...@redhat.com>
---
 drivers/net/ethernet/broadcom/bnx2.c |   27 ++++++++++++++-------------
 1 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnx2.c 
b/drivers/net/ethernet/broadcom/bnx2.c
index e838a3f..c902627 100644
--- a/drivers/net/ethernet/broadcom/bnx2.c
+++ b/drivers/net/ethernet/broadcom/bnx2.c
@@ -6202,25 +6202,26 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
         *  is setup properly */
        BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
 
-       for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
-               msix_ent[i].entry = i;
-               msix_ent[i].vector = 0;
-       }
-
        total_vecs = msix_vecs;
 #ifdef BCM_CNIC
        total_vecs++;
 #endif
-       rc = -ENOSPC;
-       while (total_vecs >= BNX2_MIN_MSIX_VEC) {
-               rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
-               if (rc <= 0)
-                       break;
-               if (rc > 0)
-                       total_vecs = rc;
+       rc = pci_msix_table_size(bp->pdev);
+       if (rc < 0)
+               return;
+
+       total_vecs = min(total_vecs, rc);
+       if (total_vecs < BNX2_MIN_MSIX_VEC)
+               return;
+
+       BUG_ON(total_vecs > ARRAY_SIZE(msix_ent));
+       for (i = 0; i < total_vecs; i++) {
+               msix_ent[i].entry = i;
+               msix_ent[i].vector = 0;
        }
 
-       if (rc != 0)
+       rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
+       if (rc)
                return;
 
        msix_vecs = total_vecs;
-- 
1.7.7.6


------------------------------------------------------------------------------
October Webinars: Code for Performance
Free Intel webinars can help you accelerate application performance.
Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from 
the latest Intel processors and coprocessors. See abstracts and register >
http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk
_______________________________________________
E1000-devel mailing list
E1000-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/e1000-devel
To learn more about Intel&#174; Ethernet, visit 
http://communities.intel.com/community/wired

Reply via email to