Doug,
I know the numbers
> will vary based on offload, etc but some general range would be a great
> place to start.
>
A couple of moths ago, I've reported such measurements of an i217 and
82574L here (thread title was: 'Descriptor writeback settings of i217'),
both on a C226 chipset. I turns out that various optimizations for
throughput or power may adversely affect the latency (the 82574 performed
way better than the i217).
>
> > What is, or even better, how do I measure transmit latency.
>
I used an Altera FPGA starter kit (
http://www.altera.com/products/devkits/altera/kit-cyclone-iv-starter.html).
The card was programmed to echo back anything on its Ethernet port (around
250ns delay) and it was also configured as a PCIe slave device with a
simple I/O port. In the Intel driver, IIRC I added a write() to the card
upon entering hard_xmit, and one right before the tail pointer write to the
NIC. In the FPGA, I recorded the sequence of events, allowing very accurate
detection of the transmit latency. With this information, it is also
possible to derive the receive latency, but you can use the PC timer to
avoid interference (PCIe transactions are costlier than reading the HPET).
I've attached the result for the 82574L with 64-byte packets at 100Mb/s.
The user_led(0) signal indicates entry in hard_xmit, user_led(1) indicates
tail pointer write update. As you can see, the driver also adds a
significant delay.
Unfortunately, I had no other NICs at hand, so I don't know how well a
82599 could or should perform.
Regards,
J.
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