> -----Original Message----- > From: Dan Carpenter [mailto:dan.carpen...@oracle.com] > Sent: Wednesday, October 01, 2014 9:52 AM > To: Duyck, Alexander H > Cc: e1000-devel@lists.sourceforge.net > Subject: re: fm10k: Add netdev > > Hello Alexander Duyck, > > The patch 0e7b36440817: "fm10k: Add netdev" from Sep 20, 2014, leads to the > following static checker warning: > > drivers/net/ethernet/intel/fm10k/fm10k_pci.c:1778 fm10k_probe() > warn: consider using resource_size() here
This is due to a limitation of the part. > drivers/net/ethernet/intel/fm10k/fm10k_pci.c > 1777 > 1778 interface->uc_addr = ioremap(pci_resource_start(pdev, 0), > 1779 FM10K_UC_ADDR_SIZE); > > FM10K_UC_ADDR_SIZE is defined like this: > > /* Defines for size of uncacheable memories */ > #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */ > #define FM10K_UC_ADDR_END 0x100000 /* end of standard regs */ > #define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - > FM10K_UC_ADDR_START) > > Everyone else in the whole world (almost) has an addressable start and end > address so you would calculate them as "end - start + 1". In this case it's > not > clear which is not addressable 0x000000 or 0x100000. > > I suspect that neither is addressable, they are misleading fake addresses > chosen > solely to fit the equation: end - start == 0x10000. > Can we pick actual start and end addresses or at least get rid of the > incorrect/misleading ones? > > regards, > dan carpenter Actually the addresses represent values within the register space. So starting at offset 0 through offset 0x0FFFFF the memory in BAR0 is just your typical un-cached memory, starting at offset 0x100000 the memory is writing combining to support features that are still in testing and may not be released, as such I didn't include the defines for the WC_ADDR_START (UC_ADDR_END), WC_ADDR_END, and WC_ADDR_SIZE. I can look at possibly renaming the end to represent the start of the write combining memory and then perhaps it will make a bit more sense. Thanks, Alex ------------------------------------------------------------------------------ Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
