On Wed, Oct 01, 2014 at 05:10:15PM +0000, Duyck, Alexander H wrote: > > Actually the addresses represent values within the register space. So > starting at offset 0 through offset 0x0FFFFF the memory in BAR0 is just your > typical un-cached memory, starting at offset 0x100000 the memory is writing > combining to support features that are still in testing and may not be > released, as such I didn't include the defines for the WC_ADDR_START > (UC_ADDR_END), WC_ADDR_END, and WC_ADDR_SIZE. I can look at possibly > renaming the end to represent the start of the write combining memory and > then perhaps it will make a bit more sense. >
Yes. That would make it more clear. regards, dan carpenter ------------------------------------------------------------------------------ Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
