Revision: 17205
http://sourceforge.net/p/edk2/code/17205
Author: erictian
Date: 2015-04-27 05:25:03 +0000 (Mon, 27 Apr 2015)
Log Message:
-----------
MdeModulePkg/XhciDxe: rename "Lenth" to "Length" in TRB structs
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>
Reviewed-by: Baraneedharan Anbazhagan <[email protected]>
Modified Paths:
--------------
trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
Modified: trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
===================================================================
--- trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c 2015-04-27 05:23:43 UTC
(rev 17204)
+++ trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c 2015-04-27 05:25:03 UTC
(rev 17205)
@@ -2,7 +2,7 @@
XHCI transfer scheduling routines.
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -295,7 +295,7 @@
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;
TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;
- TrbStart->TrbCtrSetup.Lenth = 8;
+ TrbStart->TrbCtrSetup.Length = 8;
TrbStart->TrbCtrSetup.IntTarget = 0;
TrbStart->TrbCtrSetup.IOC = 1;
TrbStart->TrbCtrSetup.IDT = 1;
@@ -321,7 +321,7 @@
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
- TrbStart->TrbCtrData.Lenth = (UINT32) Urb->DataLen;
+ TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0;
TrbStart->TrbCtrData.ISP = 1;
@@ -387,7 +387,7 @@
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy +
TotalLen);
TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy
+ TotalLen);
- TrbStart->TrbNormal.Lenth = (UINT32) Len;
+ TrbStart->TrbNormal.Length = (UINT32) Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -422,7 +422,7 @@
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy +
TotalLen);
TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy
+ TotalLen);
- TrbStart->TrbNormal.Lenth = (UINT32) Len;
+ TrbStart->TrbNormal.Length = (UINT32) Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -1137,7 +1137,7 @@
if ((TRBType == TRB_TYPE_DATA_STAGE) ||
(TRBType == TRB_TYPE_NORMAL) ||
(TRBType == TRB_TYPE_ISOCH)) {
- CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Lenth);
+ CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Length);
}
break;
Modified: trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
===================================================================
--- trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h 2015-04-27 05:23:43 UTC
(rev 17204)
+++ trunk/edk2/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h 2015-04-27 05:25:03 UTC
(rev 17205)
@@ -2,7 +2,7 @@
This file contains the definition for XHCI host controller schedule routines.
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -224,7 +224,7 @@
UINT32 TRBPtrHi;
- UINT32 Lenth:17;
+ UINT32 Length:17;
UINT32 TDSize:5;
UINT32 IntTarget:10;
@@ -253,7 +253,7 @@
UINT32 wIndex:16;
UINT32 wLength:16;
- UINT32 Lenth:17;
+ UINT32 Length:17;
UINT32 RsvdZ1:5;
UINT32 IntTarget:10;
@@ -276,7 +276,7 @@
UINT32 TRBPtrHi;
- UINT32 Lenth:17;
+ UINT32 Length:17;
UINT32 TDSize:5;
UINT32 IntTarget:10;
@@ -325,7 +325,7 @@
UINT32 TRBPtrHi;
- UINT32 Lenth:24;
+ UINT32 Length:24;
UINT32 Completecode:8;
UINT32 CycleBit:1;
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