Revision: 19286
http://sourceforge.net/p/edk2/code/19286
Author: mdkinney
Date: 2015-12-15 19:22:23 +0000 (Tue, 15 Dec 2015)
Log Message:
-----------
QuarkSocPkg: Add new package for Quark SoC X1000
Changes for V4
==============
1) Remove Unicode character from C source file
2) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
from QuarkPlatformPkg commit to QuarkSocPkg commit
Changes for V2
==============
1) Sync with new APIs in SmmCpuFeaturesLib class
2) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
3) Remove PCI serial driver from QuarkSocPkg
4) Apply optimizations to MtrrLib from MtrrLib in UefiCpuPkg
5) Convert all UNI files to utf-8
6) Replace tabs with spaces and remove trailing spaces
7) Add License.txt
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <[email protected]>
Acked-by: Jordan Justen <[email protected]>
Added Paths:
-----------
trunk/edk2/QuarkPlatformPkg/
trunk/edk2/QuarkPlatformPkg/Library/
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf
trunk/edk2/QuarkSocPkg/
trunk/edk2/QuarkSocPkg/Contributions.txt
trunk/edk2/QuarkSocPkg/License.txt
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/DdrMemoryController.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCBase.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCConfig.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCDxe.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCPeim.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCRegs.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Ppi/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Ppi/QNCMemoryInit.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PchInfo.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PlatformPolicy.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/QncS3Support.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/SmmIchnDispatch2.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/Spi.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCAccess.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCCommonDefinitions.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/CommonHeader.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/MtrrLib.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/MtrrLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/MtrrLib.uni
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/BaseAccess.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/RuntimeAccess.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/RuntimeQNCAccessLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/CommonHeader.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.uni
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInit.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInit.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/core_types.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/gen5_iosf_sb_definitions.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/general_definitions.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/hte.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/hte.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/io.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/lprint.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit_utils.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit_utils.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/memory_options.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/mrc.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/mrc.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/platform.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/prememinit.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/prememinit.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/CommonHeader.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/DxeQNCSmbus.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/DxeQNCSmbus.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/LegacyRegion.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/LegacyRegion.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInit.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInit.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCRootPorts.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCSmbus.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCSmbusExec.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/S3Support/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccessDriver.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccessDriver.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDriver.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/CommonHeader.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmGpi.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmHelpers.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmPeriodicTimer.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmQncn.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmSw.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNC/QNCSmmSx.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmm.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmCore.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmHelpers.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmHelpers.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmRegisters.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCxSmmHelpers.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Pei/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/Common/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/Common/SpiCommon.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/Common/SpiCommon.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiRuntime.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiSmm.inf
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/RuntimeDxe/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/RuntimeDxe/PchSpi.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/RuntimeDxe/PchSpi.h
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/Smm/
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/Smm/PchSpi.c
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Spi/Smm/PchSpi.h
trunk/edk2/QuarkSocPkg/QuarkSocPkg.dec
trunk/edk2/QuarkSocPkg/QuarkSocPkg.dsc
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/CEATA.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/I2cRegs.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/IohAccess.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/IohCommonDefinitions.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/Library/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/Library/I2cLib.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/Library/IohLib.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/MMC.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/SDCard.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Include/SDHostIo.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/IohInit/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/CommonHeader.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohBds.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohData.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInit.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/CommonHeader.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/I2cLib.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/I2cLib.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/CommonHeader.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/ComponentName.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/ComponentName.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/CEATA.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/CEATABlockIo.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/ComponentName.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/ComponentName.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/MMCSDBlockIo.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/MMCSDTransfer.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDevice.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDevice.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDeviceDxe.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Common/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/ComponentName.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/ComponentName.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/Descriptor.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/Ohci.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/Ohci.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDebug.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDebug.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciReg.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciReg.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciSched.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciSched.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciUrb.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciUrb.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/UsbHcMem.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/UsbHcMem.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/Descriptor.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhcPeim.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhcPeim.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciReg.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciReg.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciSched.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciSched.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciUrb.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciUrb.h
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/UsbHcMem.c
trunk/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/UsbHcMem.h
Added:
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf
===================================================================
---
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf
(rev 0)
+++
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,47 @@
+## @file
+# Library producing Pci Express Helper routines.
+#
+# Copyright (c) 2013 Intel Corporation.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD
License
+# which accompanies this distribution. The full text of the license may be
found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformPcieHelperLib
+ FILE_GUID = C153F460-5D8A-4d44-83BB-A8AF5CEF132C
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformPcieHelperLib
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformPcieHelperLib.c
+ SocUnit.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ QuarkSocPkg/QuarkSocPkg.dec
+ QuarkPlatformPkg/QuarkPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ IoLib
+ DebugLib
+ TimerLib
+ QNCAccessLib
+ IntelQNCLib
Added: trunk/edk2/QuarkSocPkg/Contributions.txt
===================================================================
--- trunk/edk2/QuarkSocPkg/Contributions.txt (rev 0)
+++ trunk/edk2/QuarkSocPkg/Contributions.txt 2015-12-15 19:22:23 UTC (rev
19286)
@@ -0,0 +1,218 @@
+
+======================
+= Code Contributions =
+======================
+
+To make a contribution to a TianoCore project, follow these steps.
+1. Create a change description in the format specified below to
+ use in the source control commit log.
+2. Your commit message must include your "Signed-off-by" signature,
+ and "Contributed-under" message.
+3. Your "Contributed-under" message explicitly states that the
+ contribution is made under the terms of the specified
+ contribution agreement. Your "Contributed-under" message
+ must include the name of contribution agreement and version.
+ For example: Contributed-under: TianoCore Contribution Agreement 1.0
+ The "TianoCore Contribution Agreement" is included below in
+ this document.
+4. Submit your code to the TianoCore project using the process
+ that the project documents on its web page. If the process is
+ not documented, then submit the code on development email list
+ for the project.
+5. It is preferred that contributions are submitted using the same
+ copyright license as the base project. When that is not possible,
+ then contributions using the following licenses can be accepted:
+ * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
+ * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
+ * MIT: http://opensource.org/licenses/MIT
+ * Python-2.0: http://opensource.org/licenses/Python-2.0
+ * Zlib: http://opensource.org/licenses/Zlib
+
+ Contributions of code put into the public domain can also be
+ accepted.
+
+ Contributions using other licenses might be accepted, but further
+ review will be required.
+
+=====================================================
+= Change Description / Commit Message / Patch Email =
+=====================================================
+
+Your change description should use the standard format for a
+commit message, and must include your "Signed-off-by" signature
+and the "Contributed-under" message.
+
+== Sample Change Description / Commit Message =
+
+=== Start of sample patch email message ===
+
+From: Contributor Name <[email protected]>
+Subject: [PATCH] CodeModule: Brief-single-line-summary
+
+Full-commit-message
+
+Contributed-under: TianoCore Contribution Agreement 1.0
+Signed-off-by: Contributor Name <[email protected]>
+---
+
+An extra message for the patch email which will not be considered part
+of the commit message can be added here.
+
+Patch content inline or attached
+
+=== End of sample patch email message ===
+
+=== Notes for sample patch email ===
+
+* The first line of commit message is taken from the email's subject
+ line following [PATCH]. The remaining portion of the commit message
+ is the email's content until the '---' line.
+* git format-patch is one way to create this format
+
+=== Definitions for sample patch email ===
+
+* "CodeModule" is a short idenfier for the affected code. For
+ example MdePkg, or MdeModulePkg UsbBusDxe.
+* "Brief-single-line-summary" is a short summary of the change.
+* The entire first line should be less than ~70 characters.
+* "Full-commit-message" a verbose multiple line comment describing
+ the change. Each line should be less than ~70 characters.
+* "Contributed-under" explicitely states that the contribution is
+ made under the terms of the contribtion agreement. This
+ agreement is included below in this document.
+* "Signed-off-by" is the contributor's signature identifying them
+ by their real/legal name and their email address.
+
+========================================
+= TianoCore Contribution Agreement 1.0 =
+========================================
+
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
+TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
+REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
+BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
+AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
+AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
+USE THE CONTENT.
+
+Unless otherwise indicated, all Content made available on the TianoCore
+site is provided to you under the terms and conditions of the BSD
+License ("BSD"). A copy of the BSD License is available at
+http://opensource.org/licenses/bsd-license.php
+or when applicable, in the associated License.txt file.
+
+Certain other content may be made available under other licenses as
+indicated in or with such Content. (For example, in a License.txt file.)
+
+You accept and agree to the following terms and conditions for Your
+present and future Contributions submitted to TianoCore site. Except
+for the license granted to Intel hereunder, You reserve all right,
+title, and interest in and to Your Contributions.
+
+== SECTION 1: Definitions ==
+* "You" or "Contributor" shall mean the copyright owner or legal
+ entity authorized by the copyright owner that is making a
+ Contribution hereunder. All other entities that control, are
+ controlled by, or are under common control with that entity are
+ considered to be a single Contributor. For the purposes of this
+ definition, "control" means (i) the power, direct or indirect, to
+ cause the direction or management of such entity, whether by
+ contract or otherwise, or (ii) ownership of fifty percent (50%)
+ or more of the outstanding shares, or (iii) beneficial ownership
+ of such entity.
+* "Contribution" shall mean any original work of authorship,
+ including any modifications or additions to an existing work,
+ that is intentionally submitted by You to the TinaoCore site for
+ inclusion in, or documentation of, any of the Content. For the
+ purposes of this definition, "submitted" means any form of
+ electronic, verbal, or written communication sent to the
+ TianoCore site or its representatives, including but not limited
+ to communication on electronic mailing lists, source code
+ control systems, and issue tracking systems that are managed by,
+ or on behalf of, the TianoCore site for the purpose of
+ discussing and improving the Content, but excluding
+ communication that is conspicuously marked or otherwise
+ designated in writing by You as "Not a Contribution."
+
+== SECTION 2: License for Contributions ==
+* Contributor hereby agrees that redistribution and use of the
+ Contribution in source and binary forms, with or without
+ modification, are permitted provided that the following
+ conditions are met:
+** Redistributions of source code must retain the Contributor's
+ copyright notice, this list of conditions and the following
+ disclaimer.
+** Redistributions in binary form must reproduce the Contributor's
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+* Disclaimer. None of the names of Contributor, Intel, or the names
+ of their respective contributors may be used to endorse or
+ promote products derived from this software without specific
+ prior written permission.
+* Contributor grants a license (with the right to sublicense) under
+ claims of Contributor's patents that Contributor can license that
+ are infringed by the Contribution (as delivered by Contributor) to
+ make, use, distribute, sell, offer for sale, and import the
+ Contribution and derivative works thereof solely to the minimum
+ extent necessary for licensee to exercise the granted copyright
+ license; this patent license applies solely to those portions of
+ the Contribution that are unmodified. No hardware per se is
+ licensed.
+* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
+ CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
+ CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ DAMAGE.
+
+== SECTION 3: Representations ==
+* You represent that You are legally entitled to grant the above
+ license. If your employer(s) has rights to intellectual property
+ that You create that includes Your Contributions, You represent
+ that You have received permission to make Contributions on behalf
+ of that employer, that Your employer has waived such rights for
+ Your Contributions.
+* You represent that each of Your Contributions is Your original
+ creation (see Section 4 for submissions on behalf of others).
+ You represent that Your Contribution submissions include complete
+ details of any third-party license or other restriction
+ (including, but not limited to, related patents and trademarks)
+ of which You are personally aware and which are associated with
+ any part of Your Contributions.
+
+== SECTION 4: Third Party Contributions ==
+* Should You wish to submit work that is not Your original creation,
+ You may submit it to TianoCore site separately from any
+ Contribution, identifying the complete details of its source
+ and of any license or other restriction (including, but not
+ limited to, related patents, trademarks, and license agreements)
+ of which You are personally aware, and conspicuously marking the
+ work as "Submitted on behalf of a third-party: [named here]".
+
+== SECTION 5: Miscellaneous ==
+* Applicable Laws. Any claims arising under or relating to this
+ Agreement shall be governed by the internal substantive laws of
+ the State of Delaware or federal courts located in Delaware,
+ without regard to principles of conflict of laws.
+* Language. This Agreement is in the English language only, which
+ language shall be controlling in all respects, and all versions
+ of this Agreement in any other language shall be for accommodation
+ only and shall not be binding. All communications and notices made
+ or given pursuant to this Agreement, and all documentation and
+ support to be provided, unless otherwise noted, shall be in the
+ English language.
+
Added: trunk/edk2/QuarkSocPkg/License.txt
===================================================================
--- trunk/edk2/QuarkSocPkg/License.txt (rev 0)
+++ trunk/edk2/QuarkSocPkg/License.txt 2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,25 @@
+Copyright (c) 2012, Intel Corporation. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/DdrMemoryController.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/DdrMemoryController.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/DdrMemoryController.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,257 @@
+/** @file
+Memory controller configuration.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __DDR_MEMORY_CONTROLLER_H__
+#define __DDR_MEMORY_CONTROLLER_H__
+
+//
+// DDR timing data definitions.
+// These are used to create bitmaps of valid timing configurations.
+//
+
+#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN 0xFF
+#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF
+
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20 0x01
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25 0x00
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30 0x02
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL 0x03
+
+
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02 0x02
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03 0x01
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04 0x00
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL 0x03
+
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02 0x02
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03 0x01
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04 0x00
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL 0x03
+
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05 0x05
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06 0x04
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07 0x03
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08 0x02
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09 0x01
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10 0x00
+#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL 0x07
+
+#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED 0x01
+#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED 0x02
+#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED 0x04
+#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED 0x08
+#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR 0x10
+#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR 0x20
+
+
+//
+// Maximum number of SDRAM channels supported by the memory controller
+//
+#define MAX_CHANNELS 1
+
+//
+// Maximum number of DIMM sockets supported by the memory controller
+//
+#define MAX_SOCKETS 1
+
+//
+// Maximum number of sides supported per DIMM
+//
+#define MAX_SIDES 2
+
+//
+// Maximum number of "Socket Sets", where a "Socket Set is a set of matching
+// DIMM's from the various channels
+//
+#define MAX_SOCKET_SETS 2
+
+//
+// Maximum number of rows supported by the memory controller
+//
+#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
+
+//
+// Maximum number of memory ranges supported by the memory controller
+//
+#define MAX_RANGES (MAX_ROWS + 5)
+
+//
+// Maximum Number of Log entries
+//
+#define MEMORY_LOG_MAX_INDEX 16
+
+
+typedef struct _MEMORY_LOG_ENTRY {
+ EFI_STATUS_CODE_VALUE Event;
+ EFI_STATUS_CODE_TYPE Severity;
+ UINT8 Data;
+} MEMORY_LOG_ENTRY;
+
+typedef struct _MEMORY_LOG {
+ UINT8 Index;
+ MEMORY_LOG_ENTRY Entry[MEMORY_LOG_MAX_INDEX];
+} MEMORY_LOG;
+
+
+
+//
+// Defined ECC types
+//
+#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE 0x01 // No error checking
+#define DUAL_CHANNEL_DDR_ECC_TYPE_EC 0x02 // Error checking
only
+#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC 0x04 // Software
Scrubbing ECC
+#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC 0x08 // Hardware
Scrubbing ECC
+#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC 0x10 // Chip Kill ECC
+
+//
+// Row configuration status values
+//
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS 0x00 // No error
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN 0x01 // Pattern mismatch,
no memory
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED 0x02 // Memory type not
supported
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR 0x03 // Row/Col/Bnk
mismatch
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR 0x04 // Received ECC error
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT 0x05 // Row is not present
+#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED 0x06 // Row is disabled
+
+
+//
+// Memory range types
+//
+typedef enum {
+ DualChannelDdrMainMemory,
+ DualChannelDdrSmramCacheable,
+ DualChannelDdrSmramNonCacheable,
+ DualChannelDdrGraphicsMemoryCacheable,
+ DualChannelDdrGraphicsMemoryNonCacheable,
+ DualChannelDdrReservedMemory,
+ DualChannelDdrMaxMemoryRangeType
+} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
+
+//
+// Memory map range information
+//
+typedef struct {
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;
+ EFI_PHYSICAL_ADDRESS CpuAddress;
+ EFI_PHYSICAL_ADDRESS RangeLength;
+ DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;
+} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
+typedef struct {
+ unsigned dramType :1; /**< Type: 0 = RESERVED; 1
= DDR2 */
+ unsigned dramWidth :1; /**< Width: 0 = x8; 1 =
x16 */
+ unsigned dramDensity :2; /**< Density: 00b = 2Gb;
01b = 1Gb; 10b = 512Mb; 11b = 256Mb */
+ unsigned dramSpeed :1; /**< Speed Grade: 0 =
RESERVED; 1 = 800MT/s;*/
+ unsigned dramTimings :3; /**< Timings: 4-4-4,
5-5-5, 6-6-6 */
+ unsigned dramRanks :1; /**< Ranks: 0 = Single
Rank; 1 = Dual Rank */
+} DramGeometry; /**< DRAM Geometry
Descriptor */
+
+typedef union _RegDRP {
+ UINT32 raw;
+ struct {
+ unsigned rank0Enabled :1; /**< Rank 0 Enable */
+ unsigned rank0DevWidth :2; /**< DRAM Device Width (x8,x16) */
+ unsigned rank0DevDensity :2; /**< DRAM Device Density
(256Mb,512Mb,1Gb,2Gb) */
+ unsigned reserved2 :1;
+ unsigned rank1Enabled :1; /**< Rank 1 Enable */
+ unsigned reserved3 :5;
+ unsigned dramType :1; /**< DRAM Type (0=DDR2) */
+ unsigned reserved4 :5;
+ unsigned reserved5 :14;
+ } field;
+} RegDRP; /**< DRAM Rank Population and
Interface Register */
+
+
+typedef union {
+ UINT32 raw;
+ struct {
+ unsigned dramFrequency :3; /**< DRAM Frequency
(000=RESERVED,010=667,011=800) */
+ unsigned tRP :2; /**< Precharge to Activate Delay
(3,4,5,6) */
+ unsigned reserved1 :1;
+ unsigned tRCD :2; /**< Activate to CAS Delay
(3,4,5,6) */
+ unsigned reserved2 :1;
+ unsigned tCL :2; /**< CAS Latency (3,4,5,6) */
+ unsigned reserved3 :21;
+ } field;
+} RegDTR0; /**< DRAM Timing Register 0 */
+
+typedef union {
+ UINT32 raw;
+ struct {
+ unsigned tWRRD_dly :2; /**< Additional Write to Read
Delay (0,1,2,3) */
+ unsigned reserved1 :1;
+ unsigned tRDWR_dly :2; /**< Additional Read to Write
Delay (0,1,2,3) */
+ unsigned reserved2 :1;
+ unsigned tRDRD_dr_dly :1; /**< Additional Read to Read Delay
(1,2) */
+ unsigned reserved3 :1;
+ unsigned tRD_dly :3; /**< Additional Read Data Sampling
Delay (0-7) */
+ unsigned reserved4 :1;
+ unsigned tRCVEN_halfclk_dly :4; /**< Additional RCVEN Half Clock
Delay Control */
+ unsigned reserved5 :1;
+ unsigned readDqDelay :2; /**< Read DQ Delay */
+ unsigned reserved6 :13;
+ } field;
+} RegDTR1; /**< DRAM Timing Register 1 */
+
+typedef union {
+ UINT32 raw;
+ struct {
+ unsigned ckStaticDisable :1; /**< CK/CK# Static Disable */
+ unsigned reserved1 :3;
+ unsigned ckeStaticDisable :2; /**< CKE Static Disable */
+ unsigned reserved2 :8;
+ unsigned refreshPeriod :2; /**< Refresh Period
(disabled,128clks,3.9us,7.8us) */
+ unsigned refreshQueueDepth :2; /**< Refresh Queue Depth (1,2,4,8)
*/
+ unsigned reserved5 :13;
+ unsigned initComplete :1; /**< Initialization Complete */
+ } field;
+} RegDCO;
+
+//
+// MRC Data Structure
+//
+typedef struct {
+ RegDRP drp;
+ RegDTR0 dtr0;
+ RegDTR1 dtr1;
+ RegDCO dco;
+ UINT32 reg0104;
+ UINT32 reg0120;
+ UINT32 reg0121;
+ UINT32 reg0123;
+ UINT32 reg0111;
+ UINT32 reg0130;
+ UINT8 refreshPeriod; /**< Placeholder for the chosen refresh
+ * period. This value will NOT be
+ * programmed into DCO until all
+ * initialization is done.
+ */
+ UINT8 ddr2Odt; /**< 0 = Disabled, 1 = 75 ohm, 2 =
150ohm, 3 = 50ohm */
+ UINT8 sku; /**< Detected QuarkNcSocId SKU */
+ UINT8 capabilities; /**< Capabilities Available on this
part */
+ UINT8 state; /**< NORMAL_BOOT, S3_RESUME */
+ UINT32 memSize; /**< Memory size */
+ UINT16 pmBase; /**< PM Base */
+ UINT16 mrcVersion; /**< MRC Version */
+ UINT32 hecbase; /**< HECBASE shifted left 16 bits */
+ DramGeometry geometry; /**< DRAM Geometry */
+} MRC_DATA_STRUCTURE; /**< QuarkNcSocId Memory Parameters for MRC
*/
+
+typedef struct _EFI_MEMINIT_CONFIG_DATA {
+ MRC_DATA_STRUCTURE MrcData;
+} EFI_MEMINIT_CONFIG_DATA;
+
+
+
+#endif
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCBase.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCBase.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCBase.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,23 @@
+/** @file
+Public include file for the QNC Base
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __INTEL_QNC_BASE_H__
+#define __INTEL_QNC_BASE_H__
+
+#include <IntelQNCRegs.h>
+#include <IntelQNCConfig.h>
+
+#endif
+
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCConfig.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCConfig.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCConfig.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,106 @@
+/** @file
+Some configuration of QNC Package
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __INTEL_QNC_CONFIG_H__
+#define __INTEL_QNC_CONFIG_H__
+
+//
+// QNC Fixed configurations.
+//
+
+//
+// Memory arbiter fixed config values.
+//
+#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\
+ (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \
+ (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \
+ (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \
+ (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \
+ ))
+
+//
+// Memory Manager fixed config values.
+//
+#define V_DRAM_NON_HOST_RQ_LIMIT 2
+
+//
+// RMU Thermal config fixed config values for TS in Vref Mode.
+//
+#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04
+#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01
+#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1
+#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b
+#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34
+
+//
+// RMU Thermal config fixed config values for TS in Ratiometric mode.
+//
+#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04
+#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02
+#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1
+#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f
+#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001
+#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01
+#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00
+#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0
+#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0
+#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8
+#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17
+
+//
+// iCLK fixed config values.
+//
+#define V_MUXTOP_FLEX2 3
+#define V_MUXTOP_FLEX1 1
+
+//
+// PCIe Root Port fixed config values.
+//
+#define V_PCIE_ROOT_PORT_SBIC_VALUE
(B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)
+
+//
+// QNC structures for configuration.
+//
+
+typedef union {
+ struct {
+ UINT32 PortErrorMask :8;
+ UINT32 SlotImplemented :1;
+ UINT32 Reserved1 :1;
+ UINT32 AspmEnable :1;
+ UINT32 AspmAutoEnable :1;
+ UINT32 AspmL0sEnable :2;
+ UINT32 AspmL1Enable :1;
+ UINT32 PmeInterruptEnable :1;
+ UINT32 PhysicalSlotNumber :13;
+ UINT32 Reserved2 :1;
+ UINT32 PmSciEnable :1;
+ UINT32 HotplugSciEnable :1;
+ } Bits;
+ UINT32 Uint32;
+} PCIEXP_ROOT_PORT_CONFIGURATION;
+
+typedef union {
+ UINT32 Uint32;
+ struct {
+ UINT32 Pcie_0 :1; // 0: Disabled; 1: Enabled*
+ UINT32 Pcie_1 :1; // 0: Disabled; 1: Enabled*
+ UINT32 Smbus :1; // 0: Disabled; 1: Enabled*
+ UINT32 Rsvd :29; // 0
+ } Bits;
+} QNC_DEVICE_ENABLES;
+
+#endif
+
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCDxe.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCDxe.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCDxe.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,23 @@
+/** @file
+Public include file for the QNC Dxe
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __INTEL_QNC_DXE_H__
+#define __INTEL_QNC_DXE_H__
+
+#include <IntelQNCRegs.h>
+#include <IntelQNCConfig.h>
+
+#endif
+
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCPeim.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCPeim.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCPeim.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,23 @@
+/** @file
+Public include file for the QNC Pei
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __INTEL_QNC_PEIM_H__
+#define __INTEL_QNC_PEIM_H__
+
+#include <IntelQNCRegs.h>
+#include <IntelQNCConfig.h>
+
+#endif
+
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCRegs.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCRegs.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/IntelQNCRegs.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,54 @@
+/** @file
+Registers definition for Intel QuarkNcSocId.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __INTEL_QNC_REGS_H__
+#define __INTEL_QNC_REGS_H__
+
+#include <QNCAccess.h>
+
+//
+// PCI HostBridge Segment number
+//
+#define QNC_PCI_HOST_BRIDGE_SEGMENT_NUMBER 0
+
+//
+// PCI RootBridge resource allocation's attribute
+//
+#define QNC_PCI_ROOT_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTE \
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
+
+//
+// PCI HostBridge resource appeture
+//
+#define QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSBASE 0x0
+#define QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSLIMIT 0xff
+#define QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_TSEG_SIZE 0x10000000
+
+//
+// PCI RootBridge configure port
+//
+#define QNC_PCI_ROOT_BRIDGE_CONFIGURATION_ADDRESS_PORT 0xCF8
+#define QNC_PCI_ROOT_BRIDGE_CONFIGURATION_DATA_PORT 0xCFC
+
+//
+// PCI Rootbridge's support feature
+//
+#define QNC_PCI_ROOT_BRIDGE_SUPPORTED
(EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \
+
EFI_PCI_ATTRIBUTE_ISA_IO | \
+
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | \
+
EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
+
EFI_PCI_ATTRIBUTE_VGA_IO)
+
+#endif // __INTEL_QNC_REGS_H__
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/IntelQNCLib.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,290 @@
+/** @file
+Library that provides QNC specific library services in PEI phase
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __INTEL_QNC_LIB_H__
+#define __INTEL_QNC_LIB_H__
+
+/**
+ This function initializes the QNC register before MRC.
+ It sets RCBA, PMBASE, disable Watchdog timer and initialize QNC GPIO.
+ If the function cannot complete it'll ASSERT().
+**/
+VOID
+EFIAPI
+PeiQNCPreMemInit (
+ VOID
+ );
+
+
+/**
+ Used to check SCH if it's S3 state. Clear the register state after query.
+
+ @retval TRUE if it's S3 state.
+ @retval FALSE if it's not S3 state.
+
+**/
+BOOLEAN
+EFIAPI
+QNCCheckS3AndClearState (
+ VOID
+ );
+
+/**
+ Used to check SCH if system wakes up from power on reset. Clear the register
state after query.
+
+ @retval TRUE if system wakes up from power on reset
+ @retval FALSE if system does not wake up from power on reset
+
+**/
+BOOLEAN
+EFIAPI
+QNCCheckPowerOnResetAndClearState (
+ VOID
+ );
+
+/**
+ This function is used to clear SMI and wake status.
+
+**/
+VOID
+EFIAPI
+QNCClearSmiAndWake (
+ VOID
+ );
+
+/**
+ Used to initialize the QNC register after MRC.
+
+**/
+VOID
+EFIAPI
+PeiQNCPostMemInit (
+ VOID
+ );
+
+/** Send DRAM Ready opcode.
+
+ @param[in] OpcodeParam Parameter to DRAM ready opcode.
+
+ @retval VOID
+**/
+VOID
+EFIAPI
+QNCSendOpcodeDramReady (
+ IN UINT32 OpcodeParam
+ );
+
+/**
+
+ Relocate RMU Main binary to memory after MRC to improve performance.
+
+ @param[in] DestBaseAddress - Specify the new memory address for the RMU
Main binary.
+ @param[in] SrcBaseAddress - Specify the current memory address for the
RMU Main binary.
+ @param[in] Size - Specify size of the RMU Main binary.
+
+ @retval VOID
+
+**/
+VOID
+EFIAPI
+RmuMainRelocation (
+ IN CONST UINT32 DestBaseAddress,
+ IN CONST UINT32 SrcBaseAddress,
+ IN CONST UINTN Size
+ );
+
+/**
+ Get the total memory size
+
+**/
+UINT32
+EFIAPI
+QNCGetTotalMemorysize (
+ VOID
+ );
+
+/**
+ Get the memory range of TSEG.
+ The TSEG's memory is below TOLM.
+
+ @param[out] BaseAddress The base address of TSEG's memory range
+ @param[out] MemorySize The size of TSEG's memory range
+
+**/
+VOID
+EFIAPI
+QNCGetTSEGMemoryRange (
+ OUT UINT64 *BaseAddress,
+ OUT UINT64 *MemorySize
+ );
+
+/**
+ Updates the PAM registers in the MCH for the requested range and mode.
+
+ @param Start The start address of the memory region
+ @param Length The length, in bytes, of the memory region
+ @param ReadEnable Pointer to the boolean variable on whether to enable
read for legacy memory section.
+ If NULL, then read attribute will not be touched by
this call.
+ @param ReadEnable Pointer to the boolean variable on whether to enable
write for legacy memory section.
+ If NULL, then write attribute will not be touched by
this call.
+ @param Granularity A pointer to granularity, in bytes, that the PAM
registers support
+
+ @retval RETURN_SUCCESS The PAM registers in the MCH were updated
+ @retval RETURN_INVALID_PARAMETER The memory range is not valid in legacy
region.
+
+**/
+RETURN_STATUS
+EFIAPI
+QNCLegacyRegionManipulation (
+ IN UINT32 Start,
+ IN UINT32 Length,
+ IN BOOLEAN *ReadEnable,
+ IN BOOLEAN *WriteEnable,
+ OUT UINT32 *Granularity
+ );
+
+/**
+ Do early init of pci express rootports on Soc.
+
+**/
+VOID
+EFIAPI
+PciExpressEarlyInit (
+ VOID
+ );
+
+/**
+ Complete initialization of all the pci express rootports on Soc.
+**/
+EFI_STATUS
+EFIAPI
+PciExpressInit (
+ );
+
+/**
+ Determine if QNC is supported.
+
+ @retval FALSE QNC is not supported.
+ @retval TRUE QNC is supported.
+**/
+BOOLEAN
+EFIAPI
+IsQncSupported (
+ VOID
+ );
+
+/**
+ Get the DeviceId of the SoC
+
+ @retval PCI DeviceId of the SoC
+**/
+UINT16
+EFIAPI
+QncGetSocDeviceId (
+ VOID
+ );
+
+/**
+ Enable SMI detection of legacy flash access violations.
+**/
+VOID
+EFIAPI
+QncEnableLegacyFlashAccessViolationSmi (
+ VOID
+ );
+
+/**
+ Setup RMU Thermal sensor registers for Vref mode.
+**/
+VOID
+EFIAPI
+QNCThermalSensorSetVRefMode (
+ VOID
+ );
+
+/**
+ Setup RMU Thermal sensor registers for Ratiometric mode.
+**/
+VOID
+EFIAPI
+QNCThermalSensorSetRatiometricMode (
+ VOID
+ );
+
+/**
+ Setup RMU Thermal sensor trip point values.
+
+ @param[in] CatastrophicTripOnDegreesCelsius - Catastrophic set trip point
threshold.
+ @param[in] HotTripOnDegreesCelsius - Hot set trip point threshold.
+ @param[in] HotTripOffDegreesCelsius - Hot clear trip point
threshold.
+
+ @retval VOID
+**/
+EFI_STATUS
+EFIAPI
+QNCThermalSensorSetTripValues (
+ IN CONST UINTN CatastrophicTripOnDegreesCelsius,
+ IN CONST UINTN HotTripOnDegreesCelsius,
+ IN CONST UINTN HotTripOffDegreesCelsius
+ );
+
+/**
+ Enable RMU Thermal sensor with a Catastrophic Trip point.
+
+ @retval EFI_SUCCESS Trip points setup.
+ @retval EFI_INVALID_PARAMETER Invalid trip point value.
+
+**/
+EFI_STATUS
+EFIAPI
+QNCThermalSensorEnableWithCatastrophicTrip (
+ IN CONST UINTN CatastrophicTripOnDegreesCelsius
+ );
+
+/**
+ Lock all RMU Thermal sensor control & trip point registers.
+
+**/
+VOID
+EFIAPI
+QNCThermalSensorLockAllRegisters (
+ VOID
+ );
+
+/**
+ Set chipset policy for double bit ECC error.
+
+ @param[in] PolicyValue Policy to config on double bit ECC error.
+
+**/
+VOID
+EFIAPI
+QNCPolicyDblEccBitErr (
+ IN CONST UINT32 PolicyValue
+ );
+
+/**
+ Determine if running on secure Quark hardware Sku.
+
+ @retval FALSE Base Quark Sku or unprovisioned Secure Sku running.
+ @retval TRUE Provisioned SecureSku hardware running.
+**/
+BOOLEAN
+EFIAPI
+QncIsSecureProvisionedSku (
+ VOID
+ );
+#endif
+
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,167 @@
+/** @file
+Library functions for Setting QNC internal network port
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __QNC_ACCESS_LIB_H__
+#define __QNC_ACCESS_LIB_H__
+
+#include <IntelQNCRegs.h>
+
+#define MESSAGE_READ_DW(Port, Reg) \
+ (UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port <<
QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) |
0xF0)
+
+#define MESSAGE_WRITE_DW(Port, Reg) \
+ (UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port <<
QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) |
0xF0)
+
+#define ALT_MESSAGE_READ_DW(Port, Reg) \
+ (UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port <<
QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) |
0xF0)
+
+#define ALT_MESSAGE_WRITE_DW(Port, Reg) \
+ (UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port <<
QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) |
0xF0)
+
+#define MESSAGE_IO_READ_DW(Port, Reg) \
+ (UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port <<
QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) |
0xF0)
+
+#define MESSAGE_IO_WRITE_DW(Port, Reg) \
+ (UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port <<
QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) |
0xF0)
+
+#define MESSAGE_SHADOW_DW(Port, Reg) \
+ (UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port <<
QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) |
0xF0)
+
+
+/**
+ Read required data from QNC internal message network
+**/
+UINT32
+EFIAPI
+QNCPortRead(
+ UINT8 Port,
+ UINT32 RegAddress
+ );
+
+/**
+ Write prepared data into QNC internal message network.
+
+**/
+VOID
+EFIAPI
+QNCPortWrite (
+ UINT8 Port,
+ UINT32 RegAddress,
+ UINT32 WriteValue
+ );
+
+/**
+ Read required data from QNC internal message network
+**/
+UINT32
+EFIAPI
+QNCAltPortRead(
+ UINT8 Port,
+ UINT32 RegAddress
+ );
+
+/**
+ Write prepared data into QNC internal message network.
+
+**/
+VOID
+EFIAPI
+QNCAltPortWrite (
+ UINT8 Port,
+ UINT32 RegAddress,
+ UINT32 WriteValue
+ );
+
+/**
+ Read required data from QNC internal message network
+**/
+UINT32
+EFIAPI
+QNCPortIORead(
+ UINT8 Port,
+ UINT32 RegAddress
+ );
+
+/**
+ Write prepared data into QNC internal message network.
+
+**/
+VOID
+EFIAPI
+QNCPortIOWrite (
+ UINT8 Port,
+ UINT32 RegAddress,
+ UINT32 WriteValue
+ );
+
+/**
+ This is for the special consideration for QNC MMIO write, as required by FWG,
+ a reading must be performed after MMIO writing to ensure the expected write
+ is processed and data is flushed into chipset
+
+**/
+RETURN_STATUS
+EFIAPI
+QNCMmIoWrite (
+ UINT32 MmIoAddress,
+ QNC_MEM_IO_WIDTH Width,
+ UINT32 DataNumber,
+ VOID *pData
+ );
+
+UINT32
+EFIAPI
+QncHsmmcRead (
+ VOID
+ );
+
+VOID
+EFIAPI
+QncHsmmcWrite (
+ UINT32 WriteValue
+ );
+
+VOID
+EFIAPI
+QncImrWrite (
+ UINT32 ImrBaseOffset,
+ UINT32 ImrLow,
+ UINT32 ImrHigh,
+ UINT32 ImrReadMask,
+ UINT32 ImrWriteMask
+ );
+
+VOID
+EFIAPI
+QncIClkAndThenOr (
+ UINT32 RegAddress,
+ UINT32 AndValue,
+ UINT32 OrValue
+ );
+
+VOID
+EFIAPI
+QncIClkOr (
+ UINT32 RegAddress,
+ UINT32 OrValue
+ );
+
+UINTN
+EFIAPI
+QncGetPciExpressBaseAddress (
+ VOID
+ );
+
+#endif
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCSmmLib.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,63 @@
+/** @file
+QNC Smm Library Services header file.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __QNC_SMM_LIB_H__
+#define __QNC_SMM_LIB_H__
+
+/**
+ This routine is the chipset code that accepts a request to "open" a region
of SMRAM.
+ The region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+ The use of "open" means that the memory is visible from all boot-service
+ and SMM agents.
+
+ @retval FALSE Cannot open a locked SMRAM region
+ @retval TRUE Success to open SMRAM region.
+**/
+BOOLEAN
+EFIAPI
+QNCOpenSmramRegion (
+ VOID
+ );
+
+/**
+ This routine is the chipset code that accepts a request to "close" a region
of SMRAM.
+ The region could be legacy AB or TSEG near top of physical memory.
+ The use of "close" means that the memory is only visible from SMM agents,
+ not from BS or RT code.
+
+ @retval FALSE Cannot open a locked SMRAM region
+ @retval TRUE Success to open SMRAM region.
+**/
+BOOLEAN
+EFIAPI
+QNCCloseSmramRegion (
+ VOID
+ );
+
+/**
+ This routine is the chipset code that accepts a request to "lock" SMRAM.
+ The region could be legacy AB or TSEG near top of physical memory.
+ The use of "lock" means that the memory can no longer be opened
+ to BS state.
+**/
+VOID
+EFIAPI
+QNCLockSmramRegion (
+ VOID
+ );
+
+
+#endif
+
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Ppi/QNCMemoryInit.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Ppi/QNCMemoryInit.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Ppi/QNCMemoryInit.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,42 @@
+/** @file
+Memory Initialization PPI used in EFI PEI interface
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __QNC_MEMORY_INIT_H__
+#define __QNC_MEMORY_INIT_H__
+
+#include "mrc.h"
+
+#define PEI_QNC_MEMORY_INIT_PPI_GUID \
+ {0x21ff1fee, 0xd33a, 0x4fce, {0xa6, 0x5e, 0x95, 0x5e, 0xa3, 0xc4, 0x1f,
0x40}}
+
+
+
+
+//
+// PPI Function Declarations
+//
+typedef
+VOID
+(EFIAPI *PEI_QNC_MEMORY_INIT) (
+ IN OUT MRCParams_t *MRCDATA
+ );
+
+typedef struct _PEI_QNC_MEMORY_INIT_PPI {
+ PEI_QNC_MEMORY_INIT MrcStart;
+}PEI_QNC_MEMORY_INIT_PPI;
+
+extern EFI_GUID gQNCMemoryInitPpiGuid;
+
+#endif
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PchInfo.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PchInfo.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PchInfo.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,54 @@
+/** @file
+This file defines the QNC Info Protocol.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+#ifndef _PCH_INFO_H_
+#define _PCH_INFO_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiQncInfoProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_QNC_INFO_PROTOCOL EFI_QNC_INFO_PROTOCOL;
+
+//
+// Protocol revision number
+// Any backwards compatible changes to this protocol will result in an update
in the revision number
+// Major changes will require publication of a new protocol
+//
+// Revision 1: Original version
+// Revision 2: Add RCVersion item to EFI_QNC_INFO_PROTOCOL
+//
+#define QNC_INFO_PROTOCOL_REVISION_1 1
+#define QNC_INFO_PROTOCOL_REVISION_2 2
+
+//
+// RCVersion[7:0] is the release number.
+//
+#define QNC_RC_VERSION 0x01020000
+
+//
+// Protocol definition
+//
+struct _EFI_QNC_INFO_PROTOCOL {
+ UINT8 Revision;
+ UINT8 BusNumber;
+ UINT32 RCVersion;
+};
+
+#endif
Added:
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PlatformPolicy.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PlatformPolicy.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/PlatformPolicy.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,37 @@
+/** @file
+Protocol used for Platform Policy definition.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#ifndef _PLATFORM_POLICY_H_
+#define _PLATFORM_POLICY_H_
+
+typedef struct _EFI_PLATFORM_POLICY_PROTOCOL EFI_PLATFORM_POLICY_PROTOCOL;
+
+#define EFI_PLATFORM_POLICY_PROTOCOL_GUID \
+ { \
+ 0x2977064f, 0xab96, 0x4fa9, { 0x85, 0x45, 0xf9, 0xc4, 0x02, 0x51, 0xe0,
0x7f } \
+ }
+
+//
+// Protocol to describe various platform information. Add to this as needed.
+//
+struct _EFI_PLATFORM_POLICY_PROTOCOL {
+ UINT8 NumRsvdSmbusAddresses;
+ UINT8 *RsvdSmbusAddresses;
+};
+
+extern EFI_GUID gEfiPlatformPolicyProtocolGuid;
+
+#endif
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/QncS3Support.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/QncS3Support.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/QncS3Support.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,90 @@
+/** @file
+This file defines the QNC S3 support Protocol.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+#ifndef _QNC_S3_SUPPORT_PROTOCOL_H_
+#define _QNC_S3_SUPPORT_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiQncS3SupportProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_QNC_S3_SUPPORT_PROTOCOL EFI_QNC_S3_SUPPORT_PROTOCOL;
+
+typedef enum {
+ QncS3ItemTypeInitPcieRootPortDownstream,
+ QncS3ItemTypeMax
+} EFI_QNC_S3_DISPATCH_ITEM_TYPE;
+
+//
+// It's better not to use pointer here because the size of pointer in DXE is
8, but it's 4 in PEI
+// plug 4 to ParameterSize in PEIM if you really need it
+//
+typedef struct {
+ UINT32 Reserved;
+} EFI_QNC_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM;
+
+typedef union {
+ EFI_QNC_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM PcieRootPortData;
+} EFI_DISPATCH_CONTEXT_UNION;
+
+typedef struct {
+ EFI_QNC_S3_DISPATCH_ITEM_TYPE Type;
+ VOID *Parameter;
+} EFI_QNC_S3_DISPATCH_ITEM;
+
+//
+// Member functions
+//
+typedef
+EFI_STATUS
+(EFIAPI *EFI_QNC_S3_SUPPORT_SET_S3_DISPATCH_ITEM) (
+ IN EFI_QNC_S3_SUPPORT_PROTOCOL * This,
+ IN EFI_QNC_S3_DISPATCH_ITEM * DispatchItem,
+ OUT VOID **S3DispatchEntryPoint,
+ OUT VOID **Context
+ );
+
+/*++
+
+Routine Description:
+
+ Set an item to be dispatched at S3 resume time. At the same time, the entry
point
+ of the QNC S3 support image is returned to be used in subsequent boot script
save
+ call
+
+Arguments:
+
+ This - Pointer to the protocol instance.
+ DispatchItem - The item to be dispatched.
+ S3DispatchEntryPoint - The entry point of the QNC S3 support image.
+
+Returns:
+
+ EFI_STATUS
+
+--*/
+
+//
+// Protocol definition
+//
+struct _EFI_QNC_S3_SUPPORT_PROTOCOL {
+ EFI_QNC_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem;
+};
+
+#endif
Added:
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/SmmIchnDispatch2.h
===================================================================
---
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/SmmIchnDispatch2.h
(rev 0)
+++
trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/SmmIchnDispatch2.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,121 @@
+/** @file
+Intel-only SMM Child Dispatcher Protocol.
+
+This protocol provides a parent dispatch service for a collection of
+chipset-specific SMI source.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __SMM_ICHN_DISPATCH2_H__
+#define __SMM_ICHN_DISPATCH2_H__
+
+//
+// Share some common definitions with Framework SMM
+//
+#include <Protocol/SmmIchnDispatch.h>
+
+#include <PiSmm.h>
+
+//
+// Global ID for the ICH SMI Protocol
+//
+#define EFI_SMM_ICHN_DISPATCH2_PROTOCOL_GUID \
+ { \
+ 0xadf3a128, 0x416d, 0x4060, {0x8d, 0xdf, 0x30, 0xa1, 0xd7, 0xaa, 0xb6,
0x99 } \
+ }
+
+typedef struct _EFI_SMM_ICHN_DISPATCH2_PROTOCOL
EFI_SMM_ICHN_DISPATCH2_PROTOCOL;
+
+typedef struct {
+ EFI_SMM_ICHN_SMI_TYPE Type;
+} EFI_SMM_ICHN_REGISTER_CONTEXT;
+
+//
+// Member functions
+//
+/**
+ Register a child SMI source dispatch function with a parent SMM driver
+
+ @param This Protocol instance pointer.
+ @param DispatchFunction Pointer to dispatch function to be invoked for
+ this SMI source
+ @param RegisterContext Pointer to the dispatch function's context.
+ The caller fills this context in before calling
+ the register function to indicate to the
register
+ function the ICHN SMI source for which the
dispatch
+ function should be invoked.
+ @param DispatchHandle Handle generated by the dispatcher to track the
+ function instance.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ registered and the SMI source has been enabled.
+ @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage
this
+ child.
+ @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The ICHN input
value
+ is not within valid range.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SMM_ICHN_DISPATCH2_REGISTER) (
+ IN CONST EFI_SMM_ICHN_DISPATCH2_PROTOCOL *This,
+ IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
+ IN OUT EFI_SMM_ICHN_REGISTER_CONTEXT *RegisterContext,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ Unregister a child SMI source dispatch function with a parent SMM driver
+
+ @param This Protocol instance pointer.
+ @param DispatchHandle Handle of dispatch function to deregister.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ unregistered and the SMI source has been
disabled
+ if there are no other registered child dispatch
+ functions for this SMI source.
+ @retval EFI_INVALID_PARAMETER Handle is invalid.
+ @retval other
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SMM_ICHN_DISPATCH2_UNREGISTER) (
+ IN EFI_SMM_ICHN_DISPATCH2_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+//
+// Interface structure for the SMM Ich n specific SMI Dispatch Protocol
+//
+/**
+ @par Protocol Description:
+ Provides a parent dispatch service for ICH SMI sources.
+
+ @param Register
+ Installs a child service to be dispatched by this protocol.
+
+ @param UnRegister
+ Removes a child service dispatched by this protocol.
+
+**/
+struct _EFI_SMM_ICHN_DISPATCH2_PROTOCOL {
+ EFI_SMM_ICHN_DISPATCH2_REGISTER Register;
+ EFI_SMM_ICHN_DISPATCH2_UNREGISTER UnRegister;
+};
+
+extern EFI_GUID gEfiSmmIchnDispatch2ProtocolGuid;
+
+#endif
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/Spi.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/Spi.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/Protocol/Spi.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,351 @@
+/** @file
+This file defines the EFI SPI Protocol which implements the
+Intel(R) ICH SPI Host Controller Compatibility Interface.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+#ifndef _SPI_H_
+#define _SPI_H_
+
+//
+// Define the SPI protocol GUID
+//
+// EDK and EDKII have different GUID formats
+//
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#define EFI_SPI_PROTOCOL_GUID \
+ { \
+ 0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13
\
+ }
+#define EFI_SMM_SPI_PROTOCOL_GUID \
+ { \
+ 0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85
\
+ }
+#else
+#define EFI_SPI_PROTOCOL_GUID \
+ { \
+ 0x1156efc6, 0xea32, 0x4396, \
+ { \
+ 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \
+ } \
+ }
+#define EFI_SMM_SPI_PROTOCOL_GUID \
+ { \
+ 0xD9072C35, 0xEB8F, 0x43ad, \
+ { \
+ 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \
+ } \
+ }
+#endif
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiSpiProtocolGuid;
+extern EFI_GUID gEfiSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+//
+// Number of Prefix Opcodes allowed on the SPI interface
+//
+#define SPI_NUM_PREFIX_OPCODE 2
+
+//
+// Number of Opcodes in the Opcode Menu
+//
+#define SPI_NUM_OPCODE 8
+
+#ifdef SERVER_BIOS_FLAG
+//
+// SPI default opcode slots
+//
+#define SPI_OPCODE_JEDEC_ID_INDEX 0
+#endif // SERVER_BIOS_FLAG
+
+//
+// Opcode Type
+// EnumSpiOpcodeCommand: Command without address
+// EnumSpiOpcodeRead: Read with address
+// EnumSpiOpcodeWrite: Write with address
+//
+typedef enum {
+ EnumSpiOpcodeReadNoAddr,
+ EnumSpiOpcodeWriteNoAddr,
+ EnumSpiOpcodeRead,
+ EnumSpiOpcodeWrite,
+ EnumSpiOpcodeMax
+} SPI_OPCODE_TYPE;
+
+typedef enum {
+ EnumSpiCycle20MHz,
+ EnumSpiCycle33MHz,
+ EnumSpiCycle66MHz, // not supported by PCH
+ EnumSpiCycle50MHz,
+ EnumSpiCycleMax
+} SPI_CYCLE_FREQUENCY;
+
+typedef enum {
+ EnumSpiRegionAll,
+ EnumSpiRegionBios,
+ EnumSpiRegionMe,
+ EnumSpiRegionGbE,
+ EnumSpiRegionDescriptor,
+ EnumSpiRegionPlatformData,
+ EnumSpiRegionMax
+} SPI_REGION_TYPE;
+
+//
+// Hardware Sequencing required operations (as listed in CougarPoint EDS Table
5-55: "Hardware
+// Sequencing Commands and Opcode Requirements"
+//
+typedef enum {
+ EnumSpiOperationWriteStatus,
+ EnumSpiOperationProgramData_1_Byte,
+ EnumSpiOperationProgramData_64_Byte,
+ EnumSpiOperationReadData,
+ EnumSpiOperationWriteDisable,
+ EnumSpiOperationReadStatus,
+ EnumSpiOperationWriteEnable,
+ EnumSpiOperationFastRead,
+ EnumSpiOperationEnableWriteStatus,
+ EnumSpiOperationErase_256_Byte,
+ EnumSpiOperationErase_4K_Byte,
+ EnumSpiOperationErase_8K_Byte,
+ EnumSpiOperationErase_64K_Byte,
+ EnumSpiOperationFullChipErase,
+ EnumSpiOperationJedecId,
+ EnumSpiOperationDualOutputFastRead,
+ EnumSpiOperationDiscoveryParameters,
+ EnumSpiOperationOther,
+ EnumSpiOperationMax
+} SPI_OPERATION;
+
+//
+// Opcode menu entries
+// Type Operation Type (value to be programmed to the OPTYPE
register)
+// Code The opcode (value to be programmed to the OPMENU register)
+// Frequency The expected frequency to be used (value to be programmed
to the SSFC
+// Register)
+// Operation Which Hardware Sequencing required operation this opcode
respoinds to.
+// The required operations are listed in EDS Table 5-55:
"Hardware
+// Sequencing Commands and Opcode Requirements"
+// If the opcode does not corresponds to any operation
listed, use
+// EnumSpiOperationOther
+//
+typedef struct _SPI_OPCODE_MENU_ENTRY {
+ SPI_OPCODE_TYPE Type;
+ UINT8 Code;
+ SPI_CYCLE_FREQUENCY Frequency;
+ SPI_OPERATION Operation;
+} SPI_OPCODE_MENU_ENTRY;
+
+//
+// Initialization data table loaded to the SPI host controller
+// VendorId Vendor ID of the SPI device
+// DeviceId0 Device ID0 of the SPI device
+// DeviceId1 Device ID1 of the SPI device
+// PrefixOpcode Prefix opcodes which are loaded into the SPI host
controller
+// OpcodeMenu Opcodes which are loaded into the SPI host controller
Opcode Menu
+// BiosStartOffset The offset of the start of the BIOS image relative to
the flash device.
+// Please note this is a Flash Linear Address, NOT a memory
space address.
+// This value is platform specific and depends on the
system flash map.
+// This value is only used on non Descriptor mode.
+// BiosSize The the BIOS Image size in flash. This value is platform
specific
+// and depends on the system flash map. Please note BIOS
Image size may
+// be smaller than BIOS Region size (in Descriptor Mode) or
the flash size
+// (in Non Descriptor Mode), and in this case, BIOS Image
is supposed to be
+// placed at the top end of the BIOS Region (in Descriptor
Mode) or the flash
+// (in Non Descriptor Mode)
+//
+typedef struct _SPI_INIT_TABLE {
+ UINT8 VendorId;
+ UINT8 DeviceId0;
+ UINT8 DeviceId1;
+ UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];
+ SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];
+ UINTN BiosStartOffset;
+ UINTN BiosSize;
+} SPI_INIT_TABLE;
+
+//
+// Public Info struct to show current initialized state of the spi interface.
+// OpcodeIndex must be less then SPI_NUM_OPCODE for operation to be supported.
+//
+typedef struct _SPI_INIT_INFO {
+ SPI_INIT_TABLE *InitTable;
+ UINT8 JedecIdOpcodeIndex;
+ UINT8 OtherOpcodeIndex;
+ UINT8 WriteStatusOpcodeIndex;
+ UINT8 ProgramOpcodeIndex;
+ UINT8 ReadOpcodeIndex;
+ UINT8 EraseOpcodeIndex;
+ UINT8 ReadStatusOpcodeIndex;
+ UINT8 FullChipEraseOpcodeIndex;
+} SPI_INIT_INFO;
+
+//
+// Protocol member functions
+//
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_INIT) (
+ IN EFI_SPI_PROTOCOL * This,
+ IN SPI_INIT_TABLE * InitTable
+ );
+/*++
+
+Routine Description:
+
+ Initializes the host controller to execute SPI commands.
+
+Arguments:
+
+ This Pointer to the EFI_SPI_PROTOCOL instance.
+ InitTable Pointer to caller-allocated buffer containing the SPI
+ interface initialization table.
+
+Returns:
+
+ EFI_SUCCESS Opcode initialization on the SPI host controller
completed.
+ EFI_ACCESS_DENIED The SPI configuration interface is locked.
+ EFI_OUT_OF_RESOURCES Not enough resource available to initialize the
device.
+ EFI_DEVICE_ERROR Device error, operation failed.
+
+--*/
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_LOCK) (
+ IN EFI_SPI_PROTOCOL * This
+ );
+/*++
+
+Routine Description:
+
+ Lock the SPI Static Configuration Interface.
+ Once locked, the interface is no longer open for configuration changes.
+ The lock state automatically clears on next system reset.
+
+Arguments:
+
+ This Pointer to the EFI_SPI_PROTOCOL instance.
+
+Returns:
+
+ EFI_SUCCESS Lock operation succeed.
+ EFI_DEVICE_ERROR Device error, operation failed.
+ EFI_ACCESS_DENIED The interface has already been locked.
+
+--*/
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_EXECUTE) (
+ IN EFI_SPI_PROTOCOL * This,
+ IN UINT8 OpcodeIndex,
+ IN UINT8 PrefixOpcodeIndex,
+ IN BOOLEAN DataCycle,
+ IN BOOLEAN Atomic,
+ IN BOOLEAN ShiftOut,
+ IN UINTN Address,
+ IN UINT32 DataByteCount,
+ IN OUT UINT8 *Buffer,
+ IN SPI_REGION_TYPE SpiRegionType
+ );
+/*++
+
+Routine Description:
+
+ Execute SPI commands from the host controller.
+
+Arguments:
+
+ This Pointer to the EFI_SPI_PROTOCOL instance.
+ OpcodeIndex Index of the command in the OpCode Menu.
+ PrefixOpcodeIndex Index of the first command to run when in an atomic
cycle sequence.
+ DataCycle TRUE if the SPI cycle contains data
+ Atomic TRUE if the SPI cycle is atomic and interleave
cycles are not allowed.
+ ShiftOut If DataByteCount is not zero, TRUE to shift data out
and FALSE to shift data in.
+ Address In Descriptor Mode, for Descriptor Region, GbE
Region, ME Region and Platform
+ Region, this value specifies the offset from the
Region Base; for BIOS Region,
+ this value specifies the offset from the start of
the BIOS Image. In Non
+ Descriptor Mode, this value specifies the offset
from the start of the BIOS Image.
+ Please note BIOS Image size may be smaller than BIOS
Region size (in Descriptor
+ Mode) or the flash size (in Non Descriptor Mode),
and in this case, BIOS Image is
+ supposed to be placed at the top end of the BIOS
Region (in Descriptor Mode) or
+ the flash (in Non Descriptor Mode)
+ DataByteCount Number of bytes in the data portion of the SPI cycle.
+ Buffer Pointer to caller-allocated buffer containing the
dada received or sent during the SPI cycle.
+ SpiRegionType SPI Region type. Values EnumSpiRegionBios,
EnumSpiRegionGbE, EnumSpiRegionMe,
+ EnumSpiRegionDescriptor, and
EnumSpiRegionPlatformData are only applicable in
+ Descriptor mode. Value EnumSpiRegionAll is
applicable to both Descriptor Mode
+ and Non Descriptor Mode, which indicates
"SpiRegionOffset" is actually relative
+ to base of the 1st flash device (i.e., it is a Flash
Linear Address).
+
+Returns:
+
+ EFI_SUCCESS Command succeed.
+ EFI_INVALID_PARAMETER The parameters specified are not valid.
+ EFI_UNSUPPORTED Command not supported.
+ EFI_DEVICE_ERROR Device error, command aborts abnormally.
+
+--*/
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_INFO) (
+ IN EFI_SPI_PROTOCOL *This,
+ OUT SPI_INIT_INFO **InitInfoPtr
+ );
+/*++
+
+Routine Description:
+
+ Return info about SPI host controller, to help callers usage of Execute
+ service.
+
+ If 0xff is returned as an opcode index in init info struct
+ then device does not support the operation.
+
+Arguments:
+
+ This Pointer to the EFI_SPI_PROTOCOL instance.
+ InitInfoPtr Pointer to init info written to this memory location.
+
+Returns:
+
+ EFI_SUCCESS Information returned.
+ EFI_INVALID_PARAMETER Invalid parameter.
+ EFI_NOT_READY Required resources not setup.
+ Others Unexpected error happened.
+
+--*/
+
+//
+// Protocol definition
+//
+struct _EFI_SPI_PROTOCOL {
+ EFI_SPI_INIT Init;
+ EFI_SPI_LOCK Lock;
+ EFI_SPI_EXECUTE Execute;
+ EFI_SPI_INFO Info;
+};
+
+#endif
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCAccess.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCAccess.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCAccess.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,183 @@
+/** @file
+Macros to simplify and abstract the interface to PCI configuration.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#ifndef _QNC_ACCESS_H_
+#define _QNC_ACCESS_H_
+
+#include "QuarkNcSocId.h"
+#include "QNCCommonDefinitions.h"
+
+#define EFI_LPC_PCI_ADDRESS( Register ) \
+ EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC,
PCI_FUNCTION_NUMBER_QNC_LPC, Register)
+
+//
+// QNC Controller PCI access macros
+//
+#define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0,
PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK)
+
+//
+// Device 0x1f, Function 0
+//
+
+#define LpcPciCfg32( Register ) \
+ QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
+
+#define LpcPciCfg32Or( Register, OrData ) \
+ QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register,
OrData )
+
+#define LpcPciCfg32And( Register, AndData ) \
+ QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register,
AndData )
+
+#define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \
+ QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0,
Register, AndData, OrData )
+
+#define LpcPciCfg16( Register ) \
+ QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
+
+#define LpcPciCfg16Or( Register, OrData ) \
+ QNCMmPci16Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register,
OrData )
+
+#define LpcPciCfg16And( Register, AndData ) \
+ QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register,
AndData )
+
+#define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \
+ QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0,
Register, AndData, OrData )
+
+#define LpcPciCfg8( Register ) \
+ QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
+
+#define LpcPciCfg8Or( Register, OrData ) \
+ QNCMmPci8Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register,
OrData )
+
+#define LpcPciCfg8And( Register, AndData ) \
+ QNCMmPci8And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register,
AndData )
+
+#define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \
+ QNCMmPci8AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0,
Register, AndData, OrData )
+
+//
+// Root Complex Register Block
+//
+
+#define MmRcrb32( Register ) \
+ QNCMmio32( QNC_RCRB_BASE, Register )
+
+#define MmRcrb32Or( Register, OrData ) \
+ QNCMmio32Or( QNC_RCRB_BASE, Register, OrData )
+
+#define MmRcrb32And( Register, AndData ) \
+ QNCMmio32And( QNC_RCRB_BASE, Register, AndData )
+
+#define MmRcrb32AndThenOr( Register, AndData, OrData ) \
+ QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
+
+#define MmRcrb16( Register ) \
+ QNCMmio16( QNC_RCRB_BASE, Register )
+
+#define MmRcrb16Or( Register, OrData ) \
+ QNCMmio16Or( QNC_RCRB_BASE, Register, OrData )
+
+#define MmRcrb16And( Register, AndData ) \
+ QNCMmio16And( QNC_RCRB_BASE, Register, AndData )
+
+#define MmRcrb16AndThenOr( Register, AndData, OrData ) \
+ QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
+
+#define MmRcrb8( Register ) \
+ QNCMmio8( QNC_RCRB_BASE, Register )
+
+#define MmRcrb8Or( Register, OrData ) \
+ QNCMmio8Or( QNC_RCRB_BASE, Register, OrData )
+
+#define MmRcrb8And( Register, AndData ) \
+ QNCMmio8And( QNC_RCRB_BASE, Register, AndData )
+
+#define MmRcrb8AndThenOr( Register, AndData, OrData ) \
+ QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
+
+//
+// Memory Controller PCI access macros
+//
+
+//
+// Device 0, Function 0
+//
+
+#define McD0PciCfg64(Register) QNCMmPci32
(0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg64Or(Register, OrData) QNCMmPci32Or
(0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg64And(Register, AndData) QNCMmPci32And
(0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg64AndThenOr(Register, AndData, OrData)
QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg32(Register) QNCMmPci32
(0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg32Or(Register, OrData) QNCMmPci32Or
(0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg32And(Register, AndData) QNCMmPci32And
(0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg32AndThenOr(Register, AndData, OrData)
QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg16(Register) QNCMmPci16
(0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg16Or(Register, OrData) QNCMmPci16Or
(0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg16And(Register, AndData) QNCMmPci16And
(0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg16AndThenOr(Register, AndData, OrData)
QNCMmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg8(Register) QNCMmPci8
(0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg8Or(Register, OrData) QNCMmPci8Or
(0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg8And(Register, AndData) QNCMmPci8And
(0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) QNCMmPci8AndThenOr
(0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+
+//
+// Memory Controller Hub Memory Mapped IO register access ???
+//
+#define MCH_REGION_BASE (McD0PciCfg64 (MC_MCHBAR_OFFSET) &
~BIT0)
+#define McMmioAddress(Register) ((UINTN) MCH_REGION_BASE + (UINTN)
(Register))
+
+#define McMmio32Ptr(Register) ((volatile UINT32*) McMmioAddress
(Register))
+#define McMmio64Ptr(Register) ((volatile UINT64*) McMmioAddress
(Register))
+
+#define McMmio64(Register) *McMmio64Ptr( Register )
+#define McMmio64Or(Register, OrData) (McMmio64 (Register) |=
(UINT64)(OrData))
+#define McMmio64And(Register, AndData) (McMmio64 (Register) &=
(UINT64)(AndData))
+#define McMmio64AndThenOr(Register, AndData, OrData) (McMmio64 ( Register ) =
(McMmio64( Register ) & (UINT64)(AndData)) | (UINT64)(OrData))
+
+#define McMmio32(Register) *McMmio32Ptr (Register)
+#define McMmio32Or(Register, OrData) (McMmio32 (Register) |=
(UINT32)(OrData))
+#define McMmio32And(Register, AndData) (McMmio32 (Register) &=
(UINT32)(AndData))
+#define McMmio32AndThenOr(Register, AndData, OrData) (McMmio32 (Register) =
(McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData))
+
+#define McMmio16Ptr(Register) ((volatile UINT16*)
McMmioAddress (Register))
+#define McMmio16(Register) *McMmio16Ptr (Register)
+#define McMmio16Or(Register, OrData) (McMmio16 (Register) |=
(UINT16) (OrData))
+#define McMmio16And(Register, AndData) (McMmio16 (Register) &=
(UINT16) (AndData))
+#define McMmio16AndThenOr(Register, AndData, OrData) (McMmio16 (Register) =
(McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData))
+
+#define McMmio8Ptr(Register) ((volatile UINT8
*)McMmioAddress (Register))
+#define McMmio8(Register) *McMmio8Ptr (Register)
+#define McMmio8Or(Register, OrData) (McMmio8 (Register) |=
(UINT8) (OrData))
+#define McMmio8And(Register, AndData) (McMmio8 (Register) &=
(UINT8) (AndData))
+#define McMmio8AndThenOr(Register, AndData, OrData) (McMmio8 (Register) =
(McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))
+
+//
+// QNC memory mapped related data structure deifinition
+//
+typedef enum {
+ QNCMmioWidthUint8 = 0,
+ QNCMmioWidthUint16 = 1,
+ QNCMmioWidthUint32 = 2,
+ QNCMmioWidthUint64 = 3,
+ QNCMmioWidthMaximum
+} QNC_MEM_IO_WIDTH;
+
+#endif
+
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCCommonDefinitions.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCCommonDefinitions.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QNCCommonDefinitions.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,356 @@
+/** @file
+This header file provides common definitions just for MCH using to avoid
including extra module's file.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _QNC_COMMON_DEFINITIONS_H_
+#define _QNC_COMMON_DEFINITIONS_H_
+
+//
+// PCI CONFIGURATION MAP REGISTER OFFSETS
+//
+#ifndef PCI_VID
+#define PCI_VID 0x0000 // Vendor ID Register
+#define PCI_DID 0x0002 // Device ID Register
+#define PCI_CMD 0x0004 // PCI Command Register
+#define PCI_STS 0x0006 // PCI Status Register
+#define PCI_RID 0x0008 // Revision ID Register
+#define PCI_IFT 0x0009 // Interface Type
+#define PCI_SCC 0x000A // Sub Class Code Register
+#define PCI_BCC 0x000B // Base Class Code Register
+#define PCI_CLS 0x000C // Cache Line Size
+#define PCI_PMLT 0x000D // Primary Master Latency Timer
+#define PCI_HDR 0x000E // Header Type Register
+#define PCI_BIST 0x000F // Built in Self Test Register
+#define PCI_BAR0 0x0010 // Base Address Register 0
+#define PCI_BAR1 0x0014 // Base Address Register 1
+#define PCI_BAR2 0x0018 // Base Address Register 2
+#define PCI_PBUS 0x0018 // Primary Bus Number Register
+#define PCI_SBUS 0x0019 // Secondary Bus Number Register
+#define PCI_SUBUS 0x001A // Subordinate Bus Number Register
+#define PCI_SMLT 0x001B // Secondary Master Latency Timer
+#define PCI_BAR3 0x001C // Base Address Register 3
+#define PCI_IOBASE 0x001C // I/O base Register
+#define PCI_IOLIMIT 0x001D // I/O Limit Register
+#define PCI_SECSTATUS 0x001E // Secondary Status Register
+#define PCI_BAR4 0x0020 // Base Address Register 4
+#define PCI_MEMBASE 0x0020 // Memory Base Register
+#define PCI_MEMLIMIT 0x0022 // Memory Limit Register
+#define PCI_BAR5 0x0024 // Base Address Register 5
+#define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register
+#define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register
+#define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32
bits
+#define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper
32 bits
+#define PCI_SVID 0x002C // Subsystem Vendor ID
+#define PCI_SID 0x002E // Subsystem ID
+#define PCI_IOBASE_U 0x0030 // I/O base Upper Register
+#define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register
+#define PCI_CAPP 0x0034 // Capabilities Pointer
+#define PCI_EROM 0x0038 // Expansion ROM Base Address
+#define PCI_INTLINE 0x003C // Interrupt Line Register
+#define PCI_INTPIN 0x003D // Interrupt Pin Register
+#define PCI_MAXGNT 0x003E // Max Grant Register
+#define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register
+#define PCI_MAXLAT 0x003F // Max Latency Register
+#endif
+//
+// Bit Difinitions
+//
+#ifndef BIT0
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#define BIT10 0x0400
+#define BIT11 0x0800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#endif
+
+
+//
+// Common Memory mapped Io access macros
------------------------------------------
+//
+#define QNCMmioAddress( BaseAddr, Register ) \
+ ( (UINTN)BaseAddr + \
+ (UINTN)(Register) \
+ )
+
+//
+// UINT64
+//
+#define QNCMmio64Ptr( BaseAddr, Register ) \
+ ( (volatile UINT64 *)QNCMmioAddress( BaseAddr, Register ) )
+
+#define QNCMmio64( BaseAddr, Register ) \
+ *QNCMmio64Ptr( BaseAddr, Register )
+
+#define QNCMmio64Or( BaseAddr, Register, OrData ) \
+ QNCMmio64( BaseAddr, Register ) = \
+ (UINT64) ( \
+ QNCMmio64( BaseAddr, Register ) | \
+ (UINT64)(OrData) \
+ )
+
+#define QNCMmio64And( BaseAddr, Register, AndData ) \
+ QNCMmio64( BaseAddr, Register ) = \
+ (UINT64) ( \
+ QNCMmio64( BaseAddr, Register ) & \
+ (UINT64)(AndData) \
+ )
+
+#define QNCMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ QNCMmio64( BaseAddr, Register ) = \
+ (UINT64) ( \
+ ( QNCMmio64( BaseAddr, Register ) & \
+ (UINT64)(AndData) \
+ ) | \
+ (UINT64)(OrData) \
+ )
+
+//
+// UINT32
+//
+#define QNCMmio32Ptr( BaseAddr, Register ) \
+ ( (volatile UINT32 *)QNCMmioAddress( BaseAddr, Register ) )
+
+#define QNCMmio32( BaseAddr, Register ) \
+ *QNCMmio32Ptr( BaseAddr, Register )
+
+#define QNCMmio32Or( BaseAddr, Register, OrData ) \
+ QNCMmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ QNCMmio32( BaseAddr, Register ) | \
+ (UINT32)(OrData) \
+ )
+
+#define QNCMmio32And( BaseAddr, Register, AndData ) \
+ QNCMmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ QNCMmio32( BaseAddr, Register ) & \
+ (UINT32)(AndData) \
+ )
+
+#define QNCMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ QNCMmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ ( QNCMmio32( BaseAddr, Register ) & \
+ (UINT32)(AndData) \
+ ) | \
+ (UINT32)(OrData) \
+ )
+//
+// UINT16
+//
+
+#define QNCMmio16Ptr( BaseAddr, Register ) \
+ ( (volatile UINT16 *)QNCMmioAddress( BaseAddr, Register ) )
+
+#define QNCMmio16( BaseAddr, Register ) \
+ *QNCMmio16Ptr( BaseAddr, Register )
+
+#define QNCMmio16Or( BaseAddr, Register, OrData ) \
+ QNCMmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ QNCMmio16( BaseAddr, Register ) | \
+ (UINT16)(OrData) \
+ )
+
+#define QNCMmio16And( BaseAddr, Register, AndData ) \
+ QNCMmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ QNCMmio16( BaseAddr, Register ) & \
+ (UINT16)(AndData) \
+ )
+
+#define QNCMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ QNCMmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ ( QNCMmio16( BaseAddr, Register ) & \
+ (UINT16)(AndData) \
+ ) | \
+ (UINT16)(OrData) \
+ )
+//
+// UINT8
+//
+#define QNCMmio8Ptr( BaseAddr, Register ) \
+ ( (volatile UINT8 *)QNCMmioAddress( BaseAddr, Register ) )
+
+#define QNCMmio8( BaseAddr, Register ) \
+ *QNCMmio8Ptr( BaseAddr, Register )
+
+#define QNCMmio8Or( BaseAddr, Register, OrData ) \
+ QNCMmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ QNCMmio8( BaseAddr, Register ) | \
+ (UINT8)(OrData) \
+ )
+
+#define QNCMmio8And( BaseAddr, Register, AndData ) \
+ QNCMmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ QNCMmio8( BaseAddr, Register ) & \
+ (UINT8)(AndData) \
+ )
+
+#define QNCMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ QNCMmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ ( QNCMmio8( BaseAddr, Register ) & \
+ (UINT8)(AndData) \
+ ) | \
+ (UINT8)(OrData) \
+ )
+
+//
+// Common Memory mapped Pci access macros
------------------------------------------
+//
+
+#define QNCMmPciAddress( Segment, Bus, Device, Function, Register ) \
+ ( (UINTN) QncGetPciExpressBaseAddress() + \
+ (UINTN)(Bus << 20) + \
+ (UINTN)(Device << 15) + \
+ (UINTN)(Function << 12) + \
+ (UINTN)(Register) \
+ )
+
+//
+// Macro to calculate the Pci device's base memory mapped address
+//
+#define PciDeviceMmBase( Bus, Device, Function) \
+ ( (UINTN) QncGetPciExpressBaseAddress () + \
+ (UINTN)(Bus << 20) + \
+ (UINTN)(Device << 15) + \
+ (UINTN)(Function << 12) \
+ )
+
+//
+// UINT32
+//
+#define QNCMmPci32Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT32 *)QNCMmPciAddress( Segment, Bus, Device, Function,
Register ) )
+
+#define QNCMmPci32( Segment, Bus, Device, Function, Register ) \
+ *QNCMmPci32Ptr( Segment, Bus, Device, Function, Register )
+
+#define QNCMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) | \
+ (UINT32)(OrData) \
+ )
+
+#define QNCMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) & \
+ (UINT32)(AndData) \
+ )
+
+#define QNCMmPci32AndThenOr( Segment, Bus, Device, Function, Register,
AndData, OrData ) \
+ QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ ( QNCMmPci32( Segment, Bus, Device, Function, Register ) & \
+ (UINT32)(AndData) \
+ ) | \
+ (UINT32)(OrData) \
+ )
+//
+// UINT16
+//
+#define QNCMmPci16Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT16 *)QNCMmPciAddress( Segment, Bus, Device, Function,
Register ) )
+
+#define QNCMmPci16( Segment, Bus, Device, Function, Register ) \
+ *QNCMmPci16Ptr( Segment, Bus, Device, Function, Register )
+
+#define QNCMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) | \
+ (UINT16)(OrData) \
+ )
+
+#define QNCMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) & \
+ (UINT16)(AndData) \
+ )
+
+#define QNCMmPci16AndThenOr( Segment, Bus, Device, Function, Register,
AndData, OrData ) \
+ QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ ( QNCMmPci16( Segment, Bus, Device, Function, Register ) & \
+ (UINT16)(AndData) \
+ ) | \
+ (UINT16)(OrData) \
+ )
+//
+// UINT8
+//
+#define QNCMmPci8Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT8 *)QNCMmPciAddress( Segment, Bus, Device, Function,
Register ) )
+
+#define QNCMmPci8( Segment, Bus, Device, Function, Register ) \
+ *QNCMmPci8Ptr( Segment, Bus, Device, Function, Register )
+
+#define QNCMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) | \
+ (UINT8)(OrData) \
+ )
+
+#define QNCMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) & \
+ (UINT8)(AndData) \
+ )
+
+#define QNCMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData,
OrData ) \
+ QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ ( QNCMmPci8( Segment, Bus, Device, Function, Register ) & \
+ (UINT8)(AndData) \
+ ) | \
+ (UINT8)(OrData) \
+ )
+
+#endif
Added: trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
===================================================================
--- trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
(rev 0)
+++ trunk/edk2/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
2015-12-15 19:22:23 UTC (rev 19286)
@@ -0,0 +1,757 @@
+/** @file
+QuarkNcSocId Register Definitions
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Definitions beginning with "R_" are registers
+Definitions beginning with "B_" are bits within registers
+Definitions beginning with "V_" are meaningful values of bits within the
registers
+Definitions beginning with "S_" are register sizes
+Definitions beginning with "N_" are the bit position
+
+**/
+
+#ifndef _QUARK_NC_SOC_ID_H_
+#define _QUARK_NC_SOC_ID_H_
+
+//
+// QNC GMCH Equates
+//
+
+//
+// DEVICE 0 (Memroy Controller Hub)
+//
+#define MC_BUS PCI_BUS_NUMBER_QNC
+#define MC_DEV 0x00
+#define MC_FUN 0x00
+
+#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID
+#define QUARK_MC_DEVICE_ID 0x0958
+#define QUARK2_MC_DEVICE_ID 0x12C0
+#define QNC_MC_REV_ID_A0 0x00
+
+
+//
+// MCR - B0:D0:F0:RD0h (WO)- Message control register
+// [31:24] Message opcode - D0 read; E0 write;
+// [23:16] Message port
+// [15:8 ] Message target register address
+// [ 7:4 ] Message write byte enable : F is enable
+// [ 3:0 ] Reserved
+//
+#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control
Register
+// Always Set to 0xF0
+
+//
+//MDR - B0:D0:F0:RD4h (RW)- Message data register
+//
+#define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register
+
+//
+//MEA - B0:D0:F0:RD8h (RW)- Message extended address register
+//
+#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended
Address Register
+
+#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode
field in MCR
+#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field
in MCR
+#define QNC_MCR_REG_OFFSET 8 // Offset of the register
field in MCR
+
+//
+// Misc Useful Macros
+//
+
+#define LShift16(value) (value << 16)
+
+//
+// QNC Message OpCodes and Attributes
+//
+#define QUARK_OPCODE_READ 0x10 // Quark message bus
"read" opcode
+#define QUARK_OPCODE_WRITE 0x11 // Quark message bus
"write" opcode
+
+//
+// Alternative opcodes for the SCSS block
+//
+#define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus
"read" opcode
+#define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus
"write" opcode
+
+//
+// QNC Message OpCodes and Attributes for IO
+//
+#define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO
read" opcode
+#define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO
write" opcode
+
+
+#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU
Main binary shadow" opcode
+
+#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management
Unit "scrub resume" opcode
+#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management
Unit "scrub pause" opcode
+
+//
+// QNC Message Ports and Registers
+//
+// Start of SB Port IDs
+#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00
+#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01
+#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03
+#define QUARK_NC_RMU_SB_PORT_ID 0x04
+#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05
+#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14
+#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16
+#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31
+#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33
+#define QUARK_ICLK_SB_PORT_ID 0x32
+#define QUARK_SCSS_CRU_SB_PORT_ID 0x34
+
+//
+// Quark Memory Arbiter Registers.
+//
+#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory
Arbiter PRI Status encodings register.
+#define ASTATUS_PRI_CASUAL 0x0 // Serviced only
if convenient
+#define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the
DRAM is in Self-Refresh.
+#define ASTATUS_PRI_NORMAL 0x2 // Normal request
servicing.
+#define ASTATUS_PRI_URGENT 0x3 // Urgent request
servicing.
+#define ASTATUS1_RASISED_BP (10)
+#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
+#define ASTATUS0_RASISED_BP (8)
+#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
+#define ASTATUS1_DEFAULT_BP (2)
+#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
+#define ASTATUS0_DEFAULT_BP (0)
+#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
+
+//
+// Quark Memory Controller Registers.
+//
+#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status
register.
+#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC.
+
+//
+// Quark Remote Management Unit Registers.
+//
+#define QNC_MSG_TMPM_REG_PMBA 0x70 // Power
Management I/O Base Address
+
+#define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote
Management Unit configuration register.
+#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)
+#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)
+
+#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote
Management Unit Options register 1.
+#define OPTIONS_1_DMA_DISABLE (BIT0)
+
+#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote
Management Unit Watchdog control register.
+#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)
+#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 <<
B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 <<
B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 <<
B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 <<
B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
+
+#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote
Management Unit Thermal sensor mode register.
+#define TS_ENABLE (BIT15)
+#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote
Management Unit Thermal sensor programmable trip point register.
+#define TS_HOT_TRIP_CLEAR_THOLD_BP 24
+#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF <<
TS_HOT_TRIP_CLEAR_THOLD_BP)
+#define TS_CAT_TRIP_CLEAR_THOLD_BP 16
+#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF <<
TS_CAT_TRIP_CLEAR_THOLD_BP)
+#define TS_HOT_TRIP_SET_THOLD_BP 8
+#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF <<
TS_HOT_TRIP_SET_THOLD_BP)
+#define TS_CAT_TRIP_SET_THOLD_BP 0
+#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF <<
TS_CAT_TRIP_SET_THOLD_BP)
+
+#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50
+#define SCRUB_CFG_INTERVAL_SHIFT 0x00
+#define SCRUB_CFG_INTERVAL_MASK 0xFF
+#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08
+#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F
+#define SCRUB_CFG_ACTIVE (BIT13)
+#define SCRUB_CFG_INVALID 0x00000FFF
+
+#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76
+#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77
+#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C
+
+#define SCRUB_RESUME_MSG() ((UINT32)( \
+ (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \
+ (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
+ 0xF0))
+
+#define SCRUB_PAUSE_MSG() ((UINT32)( \
+ (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \
+ (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
+ 0xF0))
+
+//
+// Quark Memory Manager Registers
+//
+#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82
+#define BLOCK_ENABLE_PG (1 << 28)
+#define BLOCK_DISABLE_PG (1 << 29)
+#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19
+#define EnableIMRInt BIT31
+#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C
+#define EnableSMMInt BIT31
+#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20
+#define DRAM_NON_HOST_RQ_LIMIT_BP 0
+#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f <<
DRAM_NON_HOST_RQ_LIMIT_BP)
+
+#define QUARK_NC_TOTAL_IMR_SET 0x8
+#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40
@@ Diff output truncated at 100000 characters. @@
------------------------------------------------------------------------------
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