Revision: 19287
http://sourceforge.net/p/edk2/code/19287
Author: mdkinney
Date: 2015-12-15 19:23:57 +0000 (Tue, 15 Dec 2015)
Log Message:
-----------
QuarkPlatformPkg: Add new package for Galileo boards
Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni
Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
This is required because QuarkMin.dsc uses the emulated variable
driver that does not preserve any non-volatile UEFI variables
across reset. If the condition is met where the memory type
information variable needs to be updated, then the system will reset
every time the UEFI Shell is run. By setting this PCD to FALSE,
then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
to be compatible with PACKAGES_PATH search for QuarkSocBinPkg
Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <[email protected]>
Acked-by: Jordan Justen <[email protected]>
Added Paths:
-----------
trunk/edk2/QuarkPlatformPkg/Acpi/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Facs/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc
trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/Madt.h
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/MadtPlatform.c
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.c
trunk/edk2/QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.h
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.c
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.h
trunk/edk2/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf
trunk/edk2/QuarkPlatformPkg/Contributions.txt
trunk/edk2/QuarkPlatformPkg/Include/
trunk/edk2/QuarkPlatformPkg/Include/Guid/
trunk/edk2/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h
trunk/edk2/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h
trunk/edk2/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h
trunk/edk2/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h
trunk/edk2/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h
trunk/edk2/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h
trunk/edk2/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h
trunk/edk2/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h
trunk/edk2/QuarkPlatformPkg/Include/Library/
trunk/edk2/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
trunk/edk2/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h
trunk/edk2/QuarkPlatformPkg/Include/Library/RecoveryOemHookLib.h
trunk/edk2/QuarkPlatformPkg/Include/Pcal9555.h
trunk/edk2/QuarkPlatformPkg/Include/Platform.h
trunk/edk2/QuarkPlatformPkg/Include/PlatformBoards.h
trunk/edk2/QuarkPlatformPkg/Include/Protocol/
trunk/edk2/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h
trunk/edk2/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h
trunk/edk2/QuarkPlatformPkg/Library/PlatformBootManagerLib/
trunk/edk2/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
trunk/edk2/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
trunk/edk2/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.S
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.asm
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Platform.inc
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecureLib/
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.c
trunk/edk2/QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
trunk/edk2/QuarkPlatformPkg/Library/RecoveryOemHookLib/
trunk/edk2/QuarkPlatformPkg/Library/RecoveryOemHookLib/CommonHeader.h
trunk/edk2/QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.c
trunk/edk2/QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf
trunk/edk2/QuarkPlatformPkg/License.txt
trunk/edk2/QuarkPlatformPkg/Pci/
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.c
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.h
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostResource.h
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridge.h
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridgeIo.c
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciPlatform/
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciPlatform/CommonHeader.h
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.c
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.h
trunk/edk2/QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf
trunk/edk2/QuarkPlatformPkg/Platform/
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.h
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClassStrings.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/PlatformInit/
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.h
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/CommonHeader.h
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/KeyboardLayout.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/QNCRegTable.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.h
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/Strings.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/processor.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/CommonHeader.h
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturer.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendor.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturer.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscDevicePath.h
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemString.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDevice.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignator.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturer.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionString.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignation.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationData.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationFunction.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotOnboardDevices.uni
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMisc.h
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDataTable.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscEntryPoint.c
trunk/edk2/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscStrings.uni
trunk/edk2/QuarkPlatformPkg/Platform/Pei/
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformConfig/
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf
trunk/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/FvbInfo.c
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.h
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.c
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.c
trunk/edk2/QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.h
trunk/edk2/QuarkPlatformPkg/Quark.dsc
trunk/edk2/QuarkPlatformPkg/Quark.fdf
trunk/edk2/QuarkPlatformPkg/QuarkMin.dsc
trunk/edk2/QuarkPlatformPkg/QuarkMin.fdf
trunk/edk2/QuarkPlatformPkg/QuarkPlatformPkg.dec
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,48 @@
+## @file
+# Component description file for PlatformAcpiTable module.
+#
+# Build acpi table data required by system boot.
+# All .asi files tagged with "ToolCode="DUMMY"" in following
+# file list are device description and are included by top
+# level ASL file which will be dealed with by asl.exe application.
+#
+# Copyright (c) 2013-2015 Intel Corporation.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD
License
+# which accompanies this distribution. The full text of the license may be
found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ Facs/Facs.aslc
+ Fadt/Fadt2.0.aslc
+ Hpet/Hpet.aslc
+ Mcfg/Mcfg.aslc
+ Dsdt/Platform.asl
+ CpuPm/CpuPm.asl
+ Cpu0Cst/Cpu0Cst.asl
+ Cpu0Ist/Cpu0Ist.asl
+ Cpu0Tst/Cpu0Tst.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ QuarkPlatformPkg/QuarkPlatformPkg.dec
+ QuarkSocPkg/QuarkSocPkg.dec
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,405 @@
+/** @file
+CPU C State control methods
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "Cpu0Cst.aml",
+ "SSDT",
+ 0x01,
+ "SsgPmm",
+ "Cpu0Cst",
+ 0x0011
+ )
+{
+ External(\_PR.CPU0, DeviceObj)
+ External (PDC0, IntObj)
+ External (CFGD, FieldUnitObj)
+
+ Scope(\_PR.CPU0)
+ {
+ Method (_CST, 0)
+ {
+ // If CMP is supported, and OSPM is not capable of independent C1,
P, T state
+ // support for each processor for multi-processor configuration,
we will just report
+ // C1 halt
+ //
+ // PDCx[4] = Indicates whether OSPM is not capable of independent
C1, P, T state
+ // support for each processor for multi-processor configuration.
+ //
+ If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
+ {
+ Return(Package() {
+ 1,
+ Package()
+ { // C1 halt
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ 1,
+ 157,
+ 1000
+ }
+ })
+ }
+
+ //
+ // If MWAIT extensions is supported and OSPM is capable of
performing
+ // native C state instructions for the C2/C3 in multi-processor
configuration,
+ // we report every c state with MWAIT extensions.
+ //
+ // PDCx[9] = Indicates whether OSPM is capable of performing
native C state instructions
+ // for the C2/C3 in multi-processor configuration
+ //
+ If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
+ {
+ //
+ // If C6 is supported, we report MWAIT C1,C2,C4,C6
+ //
+ If(And(CFGD,0x200))
+ {
+ Return( Package()
+ {
+ 4,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // MWAIT C2, hardware coordinated with no bus master
avoidance
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
+ 2,
+ 20,
+ 500
+ },
+ Package()
+ { // MWAIT C4, hardware coordinated with bus master
avoidance enabled
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
+ 3,
+ 100,
+ 100
+ },
+ Package()
+ { // MWAIT C6, hardware coordinated with bus master
avoidance enabled
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},
+ 3,
+ 140,
+ 10
+ }
+ })
+ }
+ //
+ // If C4 is supported, we report MWAIT C1,C2,C4
+ //
+ If(And(CFGD,0x080))
+ {
+ Return( Package()
+ {
+ 3,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // MWAIT C2, hardware coordinated with no bus master
avoidance
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
+ 2,
+ 20,
+ 500
+ },
+ Package()
+ { // MWAIT C4, hardware coordinated with bus master
avoidance enabled
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
+ 3,
+ 100,
+ 100
+ }
+ })
+ }
+ //
+ // If C2 is supported, we report MWAIT C1,C2
+ //
+ If(And(CFGD,0x020))
+ {
+ Return( Package()
+ {
+ 2,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // MWAIT C2, hardware coordinated with no bus master
avoidance
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
+ 2,
+ 20,
+ 500
+ }
+ })
+ }
+ //
+ // Else we only report MWAIT C1.
+ //
+ Return(Package()
+ {
+ 1,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ }
+ })
+ }
+
+ // If OSPM is only capable of performing native C state
instructions for
+ // the C1 in multi-processor configuration, we report C1 with
MWAIT, other
+ // C states with IO method.
+ //
+ // PDCx[8] = Indicates whether OSPM is capable of performing
native C state instructions
+ // for the C1 in multi-processor configuration
+ //
+ If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))
+ {
+ //
+ // If C6 is supported, we report MWAIT C1, IO C2,C4,C6
+ //
+ If(And(CFGD,0x200))
+ {
+ Return( Package()
+ {
+ 4,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // IO C2 ("PMBALVL2" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x324C564C41424D50)},
+ 2,
+ 20,
+ 500
+ },
+ Package()
+ { // IO C4 ("PMBALVL4" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x344C564C41424D50)},
+ 3,
+ 100,
+ 100
+ },
+ Package()
+ { // IO C6 ("PMBALVL6" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x364C564C41424D50)},
+ 3,
+ 140,
+ 10
+ }
+ })
+ }
+ //
+ // If C4 is supported, we report MWAIT C1, IO C2,C4
+ //
+ If(And(CFGD,0x080))
+ {
+ Return( Package()
+ {
+ 3,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // IO C2 ("PMBALVL2" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x324C564C41424D50)},
+ 2,
+ 20,
+ 500
+ },
+ Package()
+ { // IO C4 ("PMBALVL4" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x344C564C41424D50)},
+ 3,
+ 100,
+ 100
+ }
+ })
+ }
+ //
+ // If C2 is supported, we report MWAIT C1, IO C2
+ //
+ If(And(CFGD,0x020))
+ {
+ Return( Package()
+ {
+ 2,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // IO C2 ("PMBALVL2" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x324C564C41424D50)},
+ 2,
+ 20,
+ 500
+ }
+ })
+ }
+ //
+ // Else we only report MWAIT C1.
+ //
+ Return(Package()
+ {
+ 1,
+ Package()
+ { // MWAIT C1, hardware coordinated with no bus master
avoidance
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
+ 1,
+ 1,
+ 1000
+ }
+ })
+ }
+
+ //
+ // If MWAIT is not supported, we report all the c states with IO
method
+ //
+
+ //
+ // If C6 is supported, we report C1 halt, IO C2,C4,C6
+ //
+ If(And(CFGD,0x200))
+ {
+ Return(Package()
+ {
+ 4,
+ Package()
+ { // C1 Halt
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // IO C2 ("PMBALVL2" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x324C564C41424D50)},
+ 2,
+ 20,
+ 500
+ },
+ Package()
+ { // IO C4 ("PMBALVL4" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x344C564C41424D50)},
+ 3,
+ 100,
+ 100
+ },
+ Package()
+ { // IO C6 ("PMBALVL6" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x364C564C41424D50)},
+ 3,
+ 140,
+ 10
+ }
+ })
+ }
+ //
+ // If C4 is supported, we report C1 halt, IO C2,C4
+ //
+ If(And(CFGD,0x080))
+ {
+ Return(Package()
+ {
+ 3,
+ Package()
+ { // C1 halt
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // IO C2 ("PMBALVL2" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x324C564C41424D50)},
+ 2,
+ 20,
+ 500
+ },
+ Package()
+ { // IO C4 ("PMBALVL4" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x344C564C41424D50)},
+ 3,
+ 100,
+ 100
+ }
+ })
+ }
+
+ //
+ // If C2 is supported, we report C1 halt, IO C2
+ //
+ If(And(CFGD,0x020))
+ {
+ Return(Package()
+ {
+ 2,
+ Package()
+ { // C1 halt
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
+ 1,
+ 1,
+ 1000
+ },
+ Package()
+ { // IO C2 ("PMBALVL2" will be updated at runtime)
+ ResourceTemplate () {Register(SystemIO, 8, 0,
0x324C564C41424D50)},
+ 2,
+ 20,
+ 500
+ }
+ })
+ }
+ //
+ // Else we only report C1 halt.
+ //
+ Return(Package()
+ {
+ 1,
+ Package()
+ { // C1 halt
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
+ 1,
+ 1,
+ 1000
+ }
+ })
+ }
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,165 @@
+/** @file
+CPU EIST control methods
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "CPU0IST.aml",
+ "SSDT",
+ 0x01,
+ "SsgPmm",
+ "Cpu0Ist",
+ 0x0012
+ )
+{
+ External (PDC0, IntObj)
+ External (CFGD, FieldUnitObj)
+ External(\_PR.CPU0, DeviceObj)
+
+ Scope(\_PR.CPU0)
+ {
+ Method(_PPC,0)
+ {
+ Return(ZERO) // Return All States Available.
+ }
+
+ Method(_PCT,0)
+ {
+ //
+ // If GV3 is supported and OSPM is capable of direct access to
+ // performance state MSR, we use MSR method
+ //
+ //
+ // PDCx[0] = Indicates whether OSPM is capable of direct access to
+ // performance state MSR.
+ //
+ If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
+ {
+ Return(Package() // MSR Method
+ {
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ }
+
+ //
+ // Otherwise, we use smi method
+ //
+ Return(Package() // SMI Method
+ {
+ ResourceTemplate(){Register(SystemIO,16,0,0xB2)},
+ ResourceTemplate(){Register(SystemIO, 8,0,0xB3)}
+ })
+ }
+
+ Method(_PSS,0)
+ {
+ //
+ // If OSPM is capable of direct access to performance state MSR,
+ // we report NPSS, otherwise, we report SPSS.
+ If (And(PDC0,0x0001))
+ {
+ Return(NPSS)
+ }
+
+ Return(SPSS)
+ }
+
+ Name(SPSS,Package()
+ {
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000}
+ })
+
+ Name(NPSS,Package()
+ {
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000},
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000,
0x80000000, 0x80000000}
+ })
+
+ Method(_PSD,0)
+ {
+ //
+ // If CMP is suppored, we report the dependency with two processors
+ //
+ If(And(CFGD,0x1000000))
+ {
+ //
+ // If OSPM is capable of hardware coordination of P-states, we
report
+ // the dependency with hardware coordination.
+ //
+ // PDCx[11] = Indicates whether OSPM is capable of hardware
coordination of P-states
+ //
+ If(And(PDC0,0x0800))
+ {
+ Return(Package(){
+ Package(){
+ 5, // # entries.
+ 0, // Revision.
+ 0, // Domain #.
+ 0xFE, // Coord Type- HW_ALL.
+ 2 // # processors.
+ }
+ })
+ }
+
+ //
+ // Otherwise, the dependency with OSPM coordination
+ //
+ Return(Package(){
+ Package(){
+ 5, // # entries.
+ 0, // Revision.
+ 0, // Domain #.
+ 0xFC, // Coord Type- SW_ALL.
+ 2 // # processors.
+ }
+ })
+ }
+
+ //
+ // Otherwise, we report the dependency with one processor
+ //
+ Return(Package(){
+ Package(){
+ 5, // # entries.
+ 0, // Revision.
+ 0, // Domain #.
+ 0xFC, // Coord Type- SW_ALL.
+ 1 // # processors.
+ }
+ })
+ }
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,139 @@
+/** @file
+CPU T-state control methods
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "CPU0TST.aml",
+ "SSDT",
+ 0x01,
+ "SsgPmm",
+ "Cpu0Tst",
+ 0x0013
+ )
+{
+ External (PDC0, IntObj)
+ External (CFGD, FieldUnitObj)
+ External(\_PR.CPU0, DeviceObj)
+ External(_PSS)
+
+ Scope(\_PR.CPU0)
+ {
+ Method(_TPC,0)
+ {
+ Return(ZERO) // Return All States Available.
+ }
+
+ Name(TPTC, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC
+ })
+
+ //
+ // If OSPM is capable of direct access to on demand throttling MSR,
+ // we use MSR method;otherwise we use IO method.
+ //
+ //
+ // PDCx[2] = Indicates whether OSPM is capable of direct access to
+ // on demand throttling MSR.
+ //
+ Method(_PTC, 0)
+ {
+ If(And(PDC0, 0x0004))
+ {
+ Return(Package() // MSR Method
+ {
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ }
+ )
+ }
+ Return(Package() // IO Method
+ {
+ //
+ // PM IO base ("PMBALVL0" will be updated at runtime)
+ //
+ ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},
+ ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}
+ }
+ )
+ }
+
+ //
+ // _TSS returned package for IO Method
+ //
+ Name(TSSI, Package()
+ {
+ Package(){100, 1000, 0, 0x00, 0}
+ }
+ )
+ //
+ // _TSS returned package for MSR Method
+ //
+ Name(TSSM, Package()
+ {
+ Package(){100, 1000, 0, 0x00, 0}
+ }
+ )
+
+ Method(_TSS, 0)
+ {
+ //
+ // If OSPM is capable of direct access to on demand throttling MSR,
+ // we report TSSM;otherwise report TSSI.
+ //
+ If(And(PDC0, 0x0004))
+ {
+ Return(TSSM)
+ }
+ Return(TSSI)
+ }
+
+ Method(_TSD, 0)
+ {
+ //
+ // If CMP is suppored, we report the dependency with two processors
+ //
+ If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))
+ {
+ Return(Package()
+ {
+ Package()
+ {
+ 5, // # entries.
+ 0, // Revision.
+ 0, // Domain #.
+ 0xFD, // Coord Type- SW_ANY
+ 2 // # processors.
+ }
+ }
+ )
+ }
+ //
+ // Otherwise, we report the dependency with one processor
+ //
+ Return(Package()
+ {
+ Package()
+ {
+ 5, // # entries.
+ 0, // Revision.
+ 0, // Domain #.
+ 0xFC, // Coord Type- SW_ALL
+ 1 // # processors.
+ }
+ }
+ )
+ }
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,79 @@
+/** @file
+CPU power management control methods
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "CPUPM.aml",
+ "SSDT",
+ 0x01,
+ "SsgPmm",
+ "CpuPm",
+ 0x0010
+ )
+{
+ External(\_PR.CPU0, DeviceObj)
+ External(CFGD, FieldUnitObj)
+
+ Scope(\)
+ {
+ // Config DWord, modified during POST
+ // Bit definitions are the same as PPMFlags:
+ // CFGD[0] = PPM_GV3 = GV3
+ // CFGD[1] = PPM_TURBO = Turbo Mode
+ // CFGD[2] = PPM_SUPER_LFM = N/2 Ratio
+ // CFGD[4] = PPM_C1 = C1 Capable, Enabled
+ // CFGD[5] = PPM_C2 = C2 Capable, Enabled
+ // CFGD[6] = PPM_C3 = C3 Capable, Enabled
+ // CFGD[7] = PPM_C4 = C4 Capable, Enabled
+ // CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled
+ // CFGD[9] = PPM_C6 = C6 Capable, Enabled
+ // CFGD[10] = PPM_C1E = C1E Enabled
+ // CFGD[11] = PPM_C2E = C2E Enabled
+ // CFGD[12] = PPM_C3E = C3E Enabled
+ // CFGD[13] = PPM_C4E = C4E Enabled
+ // CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled
+ // CFGD[16] = PPM_TM1 = Thermal Monitor 1
+ // CFGD[17] = PPM_TM2 = Thermal Monitor 2
+ // CFGD[19] = PPM_PHOT = Bi-directional ProcHot
+ // CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported
+ // CFGD[24] = PPM_CMP = CMP supported, Enabled
+ // CFGD[28] = PPM_TSTATE = CPU T states supported
+ //
+ // Name(CFGD, 0x80000000)
+ // External Defined in GNVS
+
+ Name(PDC0,0x80000000) // CPU0 _PDC Flags.
+
+ // We load it in AcpiPlatform
+ //Name(SSDT,Package()
+ //{
+ // "CPU0IST ", 0x80000000, 0x80000000,
+ // "CPU1IST ", 0x80000000, 0x80000000,
+ // "CPU0CST ", 0x80000000, 0x80000000,
+ // "CPU1CST ", 0x80000000, 0x80000000,
+ //})
+ }
+ Scope(\_PR.CPU0)
+ {
+ Method(_PDC, 1)
+ {
+ //
+ // Store result of PDC.
+ //
+ CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD.
+ Store(CAP0,PDC0) // Store It in PDC0.
+ }
+ }
+
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,44 @@
+/** @file
+Analog devices AD7298 ADC.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(ADC1)
+{
+ Name(_HID, "INT3494") // Galileo Version 1 Low-Speed ADC.
+ Name(_CID, "INT3494")
+ Name(RBUF, ResourceTemplate()
+ {
+ // SPI0: mode 2, 4Mhz, 16-bit data length
+ SpiSerialBus (0x0000, PolarityLow, FourWireMode, 16,
ControllerInitiated, 4000000, ClockPolarityHigh, ClockPhaseFirst,
"\\_SB_.PCI0.SPI0",0x00, ResourceConsumer, ,)
+
+ // GPIO<0> is SPI0_CS_N
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {QUARK_GPIO0_MAPPING}
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Galileo platform has this device.
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.
+ //
+ If(LNotEqual(PTYP, 6))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,39 @@
+/** @file
+TI ADC108S102 ADC.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(ADC2)
+{
+ Name(_HID, "INT3495") // GalileoGen2 Low-Speed ADC.
+ Name(_CID, "INT3495")
+ Name(RBUF, ResourceTemplate()
+ {
+ SPISerialBus(0x0000, PolarityLow, ThreeWireMode, 0x10,
ControllerInitiated, 0x1E8480, ClockPolarityLow, ClockPhaseFirst,
"\\_SB.PCI0.SPI0", 0x00, ResourceConsumer, ,)
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,40 @@
+/** @file
+ONSEMI CAT24C08 I2C 8KB EEPROM.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(EEP2)
+{
+ Name(_HID, "INT3499") // ONSEMI CAT24C08 I2C 8KB EEPROM.
+ Name(_CID, "INT3499")
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x54, ControllerInitiated, 400000, AddressingMode7Bit,
"\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,53 @@
+/** @file
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+CY8C9540A 40 Bit I/O Expander with EEPROM.
+
+**/
+
+Device(CY8C)
+{
+ Name(_HID, "INT3490") // Cypress CY8C9540A Io Expander Function.
+ Name(_CID, "INT3490")
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x20, ControllerInitiated, 100000, AddressingMode7Bit,
"\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ GpioInt (Level, ActiveLow, Exclusive, PullDefault, ,
"\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO5_MAPPING} /*
GPIO<5> is INT_S0 */
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ CreateByteField(RBUF, 16, OB1)
+ if (LEqual (ALTS, 0))
+ {
+ Store(0x20, OB1)
+ }
+ Else
+ {
+ Store(0x21, OB1)
+ }
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Galileo platform has this device.
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.
+ //
+ If(LNotEqual(PTYP, 6))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
+
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,95 @@
+/** @file
+Expose GPIO resources to usermode through client driver.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(GPOT)
+{
+ Name(_HID, "INT349A")
+ Name(_CID, "INT349A")
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(RBUF, ResourceTemplate()
+ {
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x1}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x2}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x3}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x4}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x5}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x6}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x7}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x8}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x9}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xa}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xb}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xc}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xd}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xe}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone,
"\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xf}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x1}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x2}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x3}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x4}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x5}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x6}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x7}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x8}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x9}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0xa}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0xb}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0xc}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0xd}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0xe}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0xf}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x10}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x11}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x12}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x13}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x14}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x15}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x16}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x17}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x18}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x19}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x1a}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x1b}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x1c}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x1d}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x1e}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x1f}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x20}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x21}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x22}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x23}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x24}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x25}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x26}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C",
0, ResourceConsumer, , ) {0x27}
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Galileo platform has this device.
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.
+ //
+ If(LNotEqual(PTYP, 6))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,254 @@
+/** @file
+Legacy resource template
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef LPC_DEV_ASI
+#define LPC_DEV_ASI
+
+Device(RTC)
+{
+ Name(_HID,EISAID("PNP0B00"))
+ Name(BUF0,ResourceTemplate() {
+ IO(Decode16,0x70,0x70,0x01,0x04)
+ IO(Decode16,0x74,0x74,0x01,0x04)
+ })
+ Name(BUF1,ResourceTemplate() {
+ IO(Decode16,0x70,0x70,0x01,0x04)
+ IO(Decode16,0x74,0x74,0x01,0x04)
+ IRQNoFlags(){8}
+ })
+ Method(_CRS,0,Serialized)
+ {
+ If (HPEA)
+ {
+ return (BUF0)
+ }
+ Else
+ {
+ return (BUF1)
+ }
+ }
+}
+
+Device(PIC)
+{
+ Name(_HID,EISAID("PNP0000"))
+
+ Name(_CRS,ResourceTemplate() {
+ IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all
aliases
+ IO(Decode16,0xA0,0xA0,0x01,0x1E)
+ IO(Decode16,0x4D0,0x4D0,0x01,0x02)
+ })
+}
+
+Device(TMR)
+{
+ Name(_HID,EISAID("PNP0100"))
+
+ Name(BUF0,ResourceTemplate() {
+ IO(Decode16,0x40,0x40,0x01,0x04)
+ IO(Decode16,0x50,0x50,0x01,0x04) // alias
+ })
+ Name(BUF1,ResourceTemplate() {
+ IO(Decode16,0x40,0x40,0x01,0x04)
+ IO(Decode16,0x50,0x50,0x01,0x04) // alias
+ IRQNoFlags(){0}
+ })
+ Method(_CRS,0,Serialized)
+ {
+ If (HPEA)
+ {
+ return (BUF0)
+ }
+ Else
+ {
+ return (BUF1)
+ }
+ }
+}
+
+Device(SPKR)
+{
+ Name(_HID,EISAID("PNP0800"))
+
+ Name(_CRS,ResourceTemplate() {
+ IO(Decode16,0x61,0x61,0x01,0x01)
+ })
+}
+
+Device(XTRA) // all "PNP0C02" devices- pieces that don't fit anywhere else
+{
+ Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices
+
+ Name(CRS,
+ ResourceTemplate()
+ {
+ IO(Decode16,0x2E,0x2E,0x01,0x02)
+ IO(Decode16,0x4E,0x2E,0x01,0x02)
+ IO(Decode16,0x63,0x61,0x01,0x01)
+ IO(Decode16,0x65,0x61,0x01,0x01)
+ IO(Decode16,0x67,0x61,0x01,0x01)
+ IO(Decode16,0x80,0x80,0x01,0x01)
+ IO(Decode16,0x84,0x84,0x01,0x04)
+ IO(Decode16,0x88,0x88,0x01,0x01)
+ IO(Decode16,0x8c,0x8c,0x01,0x03)
+ IO(Decode16,0x92,0x92,0x01,0x01)
+
+ IO(
+ Decode16,
+ 0,
+ 0,
+ 0x01,
+ 0x10,
+ FIX1
+ )
+
+ IO(
+ Decode16,
+ 0,
+ 0,
+ 0x01,
+ 0x10,
+ FIX2
+ )
+
+ IO(
+ Decode16,
+ 0,
+ 0,
+ 0x01,
+ 0x40,
+ FIX3
+ )
+
+ IO(
+ Decode16,
+ 0,
+ 0,
+ 0x01,
+ 0x40,
+ FIX5
+ )
+
+ IO(
+ Decode16,
+ 0,
+ 0,
+ 0x01,
+ 0x40,
+ FIX6
+ )
+
+ }
+ )
+
+ Method (_CRS, 0, NotSerialized) {
+ CreateWordField (CRS, ^FIX1._MIN, MBR0)
+ Store(\P1BB, MBR0)
+ CreateWordField (CRS, ^FIX1._MAX, MBR1)
+ Store(\P1BB, MBR1)
+ CreateWordField (CRS, ^FIX2._MIN, MBR2)
+ Store(\PBAB, MBR2)
+ CreateWordField (CRS, ^FIX2._MAX, MBR3)
+ Store(\PBAB, MBR3)
+ CreateWordField (CRS, ^FIX3._MIN, MBR4)
+ Store(\GP0B, MBR4)
+ CreateWordField (CRS, ^FIX3._MAX, MBR5)
+ Store(\GP0B, MBR5)
+ CreateWordField (CRS, ^FIX5._MIN, MBR8)
+ Store(\SMBB, MBR8)
+ CreateWordField (CRS, ^FIX5._MAX, MBR9)
+ Store(\SMBB, MBR9)
+ CreateWordField (CRS, ^FIX6._MIN, MBRA)
+ Store(\WDTB, MBRA)
+ CreateWordField (CRS, ^FIX6._MAX, MBRB)
+ Store(\WDTB, MBRB)
+ return (CRS)
+ }
+}
+
+Device(LGIO) // Legacy GPIO.
+{
+ Name(_HID, "INT3488")
+ Name(_CID, "INT3488")
+
+ Name(CRS,
+ ResourceTemplate()
+ {
+ IO(
+ Decode16,
+ 0,
+ 0,
+ 0x01,
+ 0x48,
+ FIX4
+ )
+ }
+ )
+
+ Method (_CRS, 0, NotSerialized) {
+ CreateWordField (CRS, ^FIX4._MIN, MBR6)
+ Store(\GPAB, MBR6)
+ CreateWordField (CRS, ^FIX4._MAX, MBR7)
+ Store(\GPAB, MBR7)
+ return (CRS)
+ }
+}
+
+Device(HPET) // High Performance Event Timer
+{
+ Name(_HID,EISAID("PNP0103"))
+
+ Name(BUF0,ResourceTemplate()
+ {
+ IRQNoFlags() {0}
+ IRQNoFlags() {8}
+ Memory32Fixed(ReadOnly, 0, 0, FIX1)
+ })
+
+ Method(_STA,0)
+ {
+ // Show this Device only if the OS is WINXP or beyond.
+
+ If(LGreaterEqual(OSTP,WINDOWS_XP))
+ {
+ If(HPEA)
+ {
+ Return(0x000F) // Enabled, do Display.
+ }
+ }
+ Else
+ {
+ // OS = WIN98, WINME, or WIN2000.
+
+ If(HPEA)
+ {
+ Return(0x000B) // Enabled, don't Display.
+ }
+ }
+
+ Return(0x0000) // Return Nothing.
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ CreateDWordField (BUF0, ^FIX1._BAS, MBR0)
+ Store(\HPTB, MBR0)
+ CreateDWordField (BUF0, ^FIX1._LEN, MBR1)
+ Store(\HPTS, MBR1)
+ Return(BUF0)
+ }
+}
+
+#endif
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,40 @@
+/** @file
+NXP PCA9685 i2c-accessible PWM/LED controller.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(PWM1)
+{
+ Name(_HID, "INT3492") // NXP PCA9685 i2c-accessible PWM/LED controller.
+ Name(_CID, "INT3492")
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x47, ControllerInitiated, 400000, AddressingMode7Bit,
"\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,96 @@
+/** @file
+NXP PCAL9555A i2c-accessible I/O expander.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(NIO1)
+{
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
+ Name(_CID, "INT3491")
+ Name(_UID, 1)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x25, ControllerInitiated, 400000, AddressingMode7Bit,
"\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
+
+Device(NIO2)
+{
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
+ Name(_CID, "INT3491")
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x26, ControllerInitiated, 400000, AddressingMode7Bit,
"\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
+
+Device(NIO3)
+{
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
+ Name(_CID, "INT3491")
+ Name(_UID, 3)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x27, ControllerInitiated, 400000, AddressingMode7Bit,
"\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ GpioInt (Level, ActiveLow, Exclusive, PullDefault, ,
"\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO1_MAPPING} /*
GPIO<1> is EXP2_INT */
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,201 @@
+/** @file
+PCI Host Bridge Definitions
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+Name(PBRS, ResourceTemplate() {
+ WORDBusNumber( //Bus number resource (0); the bridge produces
bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x001f, // Max
+ 0x0000, // Translation
+ 0x0020 // Range Length = Max-Min+1
+ )
+
+ WORDIO( //Consumed-and-produced resource (all I/O below
CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0cf7, // Max
+ 0x0000, // Translation
+ 0x0cf8 // Range Length
+ )
+
+ IO( //Consumed resource (CF8-CFF)
+ Decode16,
+ 0x0cf8,
+ 0xcf8,
+ 1,
+ 8
+ )
+
+ WORDIO( //Consumed-and-produced resource (all I/O above
CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0d00, // Min
+ 0xffff, // Max
+ 0x0000, // Translation
+ 0xf300 // Range Length
+ )
+
+ DWORDMEMORY( // descriptor for dos area(0->0xa0000)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x000a0000, // Min
+ 0x000bffff, // Max
+ 0x00000000, // Translation
+ 0x00020000 // Range Length
+ )
+
+ DWORDMemory( // Consumed-and-produced resource for pci memory
mapped memory
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Min (calculated dynamically)
+
+ 0xfebfffff, // Max = IO Apic base address - 1
+ 0x00000000, // Translation
+ 0xfec00000, // Range Length (calculated dynamically)
+ , // Optional field left blank
+ , // Optional field left blank
+ MEM1 // Name declaration for this descriptor
+ )
+
+}) // end of CRES Buffer
+
+
+Method(_CRS, 0x0, NotSerialized)
+{
+ CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)
+ CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)
+ CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)
+
+ // HMBOUND is PCI memory base
+ And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)
+ Add(Subtract(MMAX, MMIN), 1, MLEN)
+
+ Return(PBRS)
+}
+
+// Message Nework Registers
+OperationRegion(MNR, PCI_Config, 0xD0, 0x10)
+Field(MNR, DWordAcc, NoLock, Preserve)
+{
+ MCR, 32, // Message Control Register
+ MDR, 32 // Message Data Register
+}
+
+// Message Nework Read Method
+// Arg0 = Port
+// Arg1 = RegAddress
+// return 32 bit register value
+Method(MNRD, 2, Serialized)
+{
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
+ Or(Local0, 0x100000F0, Local0)
+ Store(Local0, MCR)
+ Return(MDR)
+}
+
+// Message Nework Write Method
+// Arg0 = Port
+// Arg1 = RegAddress
+// Arg2 = 32 bit write value
+Method(MNWR, 3, Serialized)
+{
+ Store(Arg2, MDR)
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
+ Or(Local0, 0x110000F0, Local0)
+ Store(Local0, MCR)
+}
+
+Method(_PRT, 0, NotSerialized)
+{
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
+ {
+ Return (
+ Package()
+ {
+ // Bus 0, Device 20 - IOSFAHB Bridge
+ Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
+ Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
+ Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
+ Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
+
+ // Bus 0, Device 21 - IOSFAHB Bridge
+ Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
+ Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
+ Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
+ Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
+
+ // Bus 0, Device 23 - PCIe port 0
+ Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA
+ Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB
+ Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC
+ Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD
+
+ // Bus 0, Device 31
+ Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge
+ }
+ )
+ }
+ else {
+ Return (
+ Package()
+ {
+ // Bus 0, Device 20 - IOSFAHB Bridge
+ Package() {0x0014ffff, 0, 0, 16}, // INTA
+ Package() {0x0014ffff, 1, 0, 17}, // INTB
+ Package() {0x0014ffff, 2, 0, 18}, // INTC
+ Package() {0x0014ffff, 3, 0, 19}, // INTD
+
+ // Bus 0, Device 21 - IOSFAHB Bridge
+ Package() {0x0015ffff, 0, 0, 16}, // INTA
+ Package() {0x0015ffff, 1, 0, 17}, // INTB
+ Package() {0x0015ffff, 2, 0, 18}, // INTC
+ Package() {0x0015ffff, 3, 0, 19}, // INTD
+
+ // Bus 0, Device 23 - PCIe port 0
+ Package() {0x0017ffff, 0, 0, 20}, // INTA
+ Package() {0x0017ffff, 1, 0, 21}, // INTB
+ Package() {0x0017ffff, 2, 0, 22}, // INTC
+ Package() {0x0017ffff, 3, 0, 23}, // INTD
+
+ // Bus 0, Device 31
+ Package() {0x001fffff, 0, 0, 16}, // LPC Bridge
+ }
+ )
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,558 @@
+/** @file
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+// Interrupts can be DEB8=all except 13,8,6,2,1,0
+
+#ifndef PCIIRQ_ASI
+#define PCIIRQ_ASI
+
+OperationRegion(PRR0, PCI_Config, 0x60, 0x08)
+Field(PRR0, ANYACC, NOLOCK, PRESERVE)
+{
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8,
+ PIRE, 8,
+ PIRF, 8,
+ PIRG, 8,
+ PIRH, 8
+}
+
+Device(LNKA) // PCI IRQ link A
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 1)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRA, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRA, 0x80, PIRA)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+
+ // Define references to buffer elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ descriptor
+ If (And(PIRA, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ }
+ // Shift 1 by value in
register 70
+ ShiftLeft(Local0,And(PIRA,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else
+ {
+ Or(Local0, 0x80,Local0)
+ }
+ store(Local0, PIRA)
+ } // End of _SRS Method
+}
+
+Device(LNKB) // PCI IRQ link B
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 2)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRB, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRB, 0x80,PIRB)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ // Define references to buffer
elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ
descriptor
+ If (And(PIRB, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ }
+ // Shift 1 by value in register
70
+ ShiftLeft(Local0,And(PIRB,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else
+ {
+ Or(Local0, 0x80,Local0)
+ }
+ Store(Local0, PIRB)
+ } // End of _SRS Method
+}
+
+Device(LNKC) // PCI IRQ link C
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 3)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRC, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRC, 0x80,PIRC)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ // Define references to buffer
elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ
descriptor
+ If (And(PIRC, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ } // Shift 1 by value in register
70
+ ShiftLeft(Local0,And(PIRC,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else {
+ Or(Local0, 0x80,Local0)
+ }
+ Store(Local0, PIRC)
+ } // End of _SRS Method
+}
+
+Device(LNKD) // PCI IRQ link D
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 4)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRD, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRD, 0x80,PIRD)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ // Define references to buffer elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ descriptor
+ If (And(PIRD, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ } // Shift 1 by value in register 70
+ ShiftLeft(Local0,And(PIRD,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0)// Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else
+ {
+ Or(Local0, 0x80,Local0)
+ }
+ Store(Local0, PIRD)
+ } // End of _SRS Method
+}
+
+Device(LNKE) // PCI IRQ link E
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 5)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRE, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRE, 0x80, PIRE)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+
+ // Define references to buffer elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ descriptor
+ If (And(PIRE, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ }
+ // Shift 1 by value in
register 70
+ ShiftLeft(Local0,And(PIRE,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else
+ {
+ Or(Local0, 0x80,Local0)
+ }
+ store(Local0, PIRE)
+ } // End of _SRS Method
+}
+
+Device(LNKF) // PCI IRQ link F
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 6)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRF, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRB, 0x80,PIRF)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ // Define references to buffer
elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ
descriptor
+ If (And(PIRF, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ }
+ // Shift 1 by value in register
70
+ ShiftLeft(Local0,And(PIRF,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else
+ {
+ Or(Local0, 0x80,Local0)
+ }
+ Store(Local0, PIRF)
+ } // End of _SRS Method
+}
+
+Device(LNKG) // PCI IRQ link G
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 7)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRG, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRG, 0x80,PIRG)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ // Define references to buffer
elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ
descriptor
+ If (And(PIRG, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ } // Shift 1 by value in register
70
+ ShiftLeft(Local0,And(PIRG,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else {
+ Or(Local0, 0x80,Local0)
+ }
+ Store(Local0, PIRG)
+ } // End of _SRS Method
+}
+
+Device(LNKH) // PCI IRQ link H
+{
+ Name(_HID,EISAID("PNP0C0F"))
+
+ Name(_UID, 8)
+
+ Method(_STA,0,NotSerialized)
+ {
+ If(And(PIRH, 0x80))
+ {
+ Return(0x9)
+ }
+ Else
+ {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method(_DIS,0,NotSerialized)
+ {
+ Or(PIRH, 0x80,PIRH)
+ }
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ // Define references to buffer elements
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ // Write current settings into IRQ descriptor
+ If (And(PIRH, 0x80))
+ {
+ Store(Zero, Local0)
+ }
+ Else
+ {
+ Store(One,Local0)
+ } // Shift 1 by value in register 70
+ ShiftLeft(Local0,And(PIRH,0x0F),IRQW) // Save in buffer
+ Return(BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})
+
+ Method(_SRS,1,NotSerialized)
+ {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0)// Set IRQ
+ If (LNotEqual(IRQW,Zero))
+ {
+ And(Local0, 0x7F,Local0)
+ Decrement(Local0)
+ }
+ Else
+ {
+ Or(Local0, 0x80,Local0)
+ }
+ Store(Local0, PIRH)
+ } // End of _SRS Method
+}
+
+#endif
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,133 @@
+/** @file
+PCI express expansion ports
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PcieExpansionPrt_asi
+#define PcieExpansionPrt_asi
+
+Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0]
+{
+ Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0
+ Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
+
+ OperationRegion (PES0,PCI_Config,0x40,0xA0)
+ Field (PES0, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x1A), // SLSTS - Slot Status Register
+ ABP0, 1, // Bit 0, Attention Button Pressed
+ , 2,
+ PDC0, 1, // Bit 3, Presence Detect Changed
+ , 2,
+ PDS0, 1, // Bit 6, Presence Detect State
+ , 1,
+ LSC0, 1, // Bit 8, Link Active State Changed
+ offset (0x20),
+ , 16,
+ PMS0, 1, // Bit 16, PME Status
+ offset (0x98),
+ , 30,
+ HPE0, 1, // Bit 30, Hot Plug SCI Enable
+ PCE0, 1, // Bit 31, Power Management SCI Enable.
+ , 30,
+ HPS0, 1, // Bit 30, Hot Plug SCI Status
+ PCS0, 1, // Bit 31, Power Management SCI Status.
+ }
+
+ Method(_PRT,0,NotSerialized) {
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
+ Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI
Slot 1
+ Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},
+ Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},
+ Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},
+ }
+ )
+ }
+ else // IOAPIC Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
+ Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1
+ Package() {0x0000ffff, 1, 0, 21},
+ Package() {0x0000ffff, 2, 0, 22},
+ Package() {0x0000ffff, 3, 0, 23},
+ }
+ )
+ }
+ }
+}
+
+Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1]
+{
+ Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1
+ Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
+ OperationRegion (PES1,PCI_Config,0x40,0xA0)
+ Field (PES1, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x1A), // SLSTS - Slot Status Register
+ ABP1, 1, // Bit 0, Attention Button Pressed
+ , 2,
+ PDC1, 1, // Bit 3, Presence Detect Changed
+ , 2,
+ PDS1, 1, // Bit 6, Presence Detect State
+ , 1,
+ LSC1, 1, // Bit 8, Link Active State Changed
+ offset (0x20),
+ , 16,
+ PMS1, 1, // Bit 16, PME Status
+ offset (0x98),
+ , 30,
+ HPE1, 1, // Bit 30, Hot Plug SCI Enable
+ PCE1, 1, // Bit 31, Power Management SCI Enable.
+ , 30,
+ HPS1, 1, // Bit 30, Hot Plug SCI Status
+ PCS1, 1, // Bit 31, Power Management SCI Status.
+ }
+ Method(_PRT,0,NotSerialized) {
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
+ Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},
+ Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},
+ Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},
+ Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},
+ }
+ )
+ }
+ else // IOAPIC Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
+ Package() {0x0000ffff, 0, 0, 21},
+ Package() {0x0000ffff, 1, 0, 22},
+ Package() {0x0000ffff, 2, 0, 23},
+ Package() {0x0000ffff, 3, 0, 20},
+ }
+ )
+ }
+ }
+}
+
+#endif
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,353 @@
+/** @file
+Contains root level name space objects for the platform
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// OS TYPE DEFINITION
+//
+#define WINDOWS_XP 0x01
+#define WINDOWS_XP_SP1 0x02
+#define WINDOWS_XP_SP2 0x04
+#define WINDOWS_2003 0x08
+#define WINDOWS_Vista 0x10
+#define WINDOWS_WIN7 0x11
+#define WINDOWS_WIN8 0x12
+#define WINDOWS_WIN8_1 0x13
+#define LINUX 0xF0
+
+//
+// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.
+// GpioInt() descriptors maybe used in this file and included .asi files.
+//
+// The mapping below was provided by the first OS user that requested
+// GpioInt() support.
+// Other OS users that need GpioInt() support must use the following mapping.
+//
+#define QUARK_GPIO8_MAPPING 0x00
+#define QUARK_GPIO9_MAPPING 0x01
+#define QUARK_GPIO_SUS0_MAPPING 0x02
+#define QUARK_GPIO_SUS1_MAPPING 0x03
+#define QUARK_GPIO_SUS2_MAPPING 0x04
+#define QUARK_GPIO_SUS3_MAPPING 0x05
+#define QUARK_GPIO_SUS4_MAPPING 0x06
+#define QUARK_GPIO_SUS5_MAPPING 0x07
+#define QUARK_GPIO0_MAPPING 0x08
+#define QUARK_GPIO1_MAPPING 0x09
+#define QUARK_GPIO2_MAPPING 0x0A
+#define QUARK_GPIO3_MAPPING 0x0B
+#define QUARK_GPIO4_MAPPING 0x0C
+#define QUARK_GPIO5_MAPPING 0x0D
+#define QUARK_GPIO6_MAPPING 0x0E
+#define QUARK_GPIO7_MAPPING 0x0F
+
+DefinitionBlock (
+ "Platform.aml",
+ "DSDT",
+ 1,
+ "INTEL ",
+ "QuarkNcSocId",
+ 3)
+{
+ //
+ // Global Variables
+ //
+ Name(\GPIC, 0x0)
+
+ //
+ // Port 80
+ //
+ OperationRegion (DBG0, SystemIO, 0x80, 1)
+ Field (DBG0, ByteAcc, NoLock, Preserve)
+ { IO80,8 }
+
+ //
+ // Access CMOS range
+ //
+ OperationRegion (ACMS, SystemIO, 0x72, 2)
+ Field (ACMS, ByteAcc, NoLock, Preserve)
+ { INDX, 8, DATA, 8 }
+
+ //
+ // Global NVS Memory Block
+ //
+ OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)
+ Field (MNVS, ByteAcc, NoLock, Preserve)
+ {
+ OSTP, 32,
+ CFGD, 32,
+ HPEA, 32, // HPET Enabled ?
+
+ P1BB, 32, // Pm1blkIoBaseAddress;
+ PBAB, 32, // PmbaIoBaseAddress;
+ GP0B, 32, // Gpe0blkIoBaseAddress;
+ GPAB, 32, // GbaIoBaseAddress;
+
+ SMBB, 32, // SmbaIoBaseAddress;
+ NRV1, 32, // GNVS reserved field 1.
+ WDTB, 32, // WdtbaIoBaseAddress;
+
+ HPTB, 32, // HpetBaseAddress;
+ HPTS, 32, // HpetSize;
+ PEXB, 32, // PciExpressBaseAddress;
+ PEXS, 32, // PciExpressSize;
+
+ RCBB, 32, // RcbaMmioBaseAddress;
+ RCBS, 32, // RcbaMmioSize;
+ APCB, 32, // IoApicBaseAddress;
+ APCS, 32, // IoApicSize;
+
+ TPMP, 32, // TpmPresent ?
+ DBGP, 32, // DBG2 Present?
+ PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.
+ ALTS, 32, // Use alternate I2c SLA addresses.
+ }
+
+ OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block
+ Field (GPEB, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x10),
+ SMIE, 32, // SMI Enable
+ SMIS, 32, // SMI Status
+ }
+
+ //
+ // Processor Objects
+ //
+ Scope(\_PR) {
+ //
+ // IO base will be updated at runtime with search key "PRIO"
+ //
+ Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
+ }
+
+ //
+ // System Sleep States
+ //
+ Name (\_S0,Package (){0,0,0,0})
+ Name (\_S3,Package (){5,0,0,0})
+ Name (\_S4,Package (){6,0,0,0})
+ Name (\_S5,Package (){7,0,0,0})
+
+ //
+ // General Purpose Event
+ //
+ Scope(\_GPE)
+ {
+ //
+ // EGPE generated GPE
+ //
+ Method(_L0D, 0x0, NotSerialized)
+ {
+ //
+ // Check EGPE for this wake event
+ //
+ Notify (\_SB.SLPB, 0x02)
+
+ }
+
+ //
+ // GPIO generated GPE
+ //
+ Method(_L0E, 0x0, NotSerialized)
+ {
+ //
+ // Check GPIO for this wake event
+ //
+ Notify (\_SB.PWRB, 0x02)
+
+ }
+
+ //
+ // SCLT generated GPE
+ //
+ Method(_L0F, 0x0, NotSerialized)
+ {
+ //
+ // Check SCLT for this wake event
+ //
+ Notify (\_SB.PCI0.SDIO, 0x02)
+ Notify (\_SB.PCI0.URT0, 0x02)
+ Notify (\_SB.PCI0.USBD, 0x02)
+ Notify (\_SB.PCI0.EHCI, 0x02)
+ Notify (\_SB.PCI0.OHCI, 0x02)
+ Notify (\_SB.PCI0.URT1, 0x02)
+ Notify (\_SB.PCI0.ENT0, 0x02)
+ Notify (\_SB.PCI0.ENT1, 0x02)
+ Notify (\_SB.PCI0.SPI0, 0x02)
+ Notify (\_SB.PCI0.SPI1, 0x02)
+ Notify (\_SB.PCI0.GIP0, 0x02)
+
+ }
+
+ //
+ // Remote Management Unit generated GPE
+ //
+ Method(_L10, 0x0, NotSerialized)
+ {
+ //
+ // Check Remote Management Unit for this wake event.
+ //
+ }
+
+ //
+ // PCIE generated GPE
+ //
+ Method(_L11, 0x0, NotSerialized)
+ {
+ //
+ // Check PCIE for this wake event
+ //
+ Notify (\_SB.PCI0.PEX0, 0x02)
+ Notify (\_SB.PCI0.PEX1, 0x02)
+ }
+ }
+
+ //
+ // define Sleeping button as mentioned in ACPI spec 2.0
+ //
+ Device (\_SB.SLPB)
+ {
+ Name (_HID, EISAID ("PNP0C0E"))
+ Method (_PRW, 0, NotSerialized)
+ {
+ Return (Package (0x02) {0x0D,0x04})
+ }
+ }
+
+ //
+ // define Power Button
+ //
+ Device (\_SB.PWRB)
+ {
+ Name (_HID, EISAID ("PNP0C0C"))
+ Method (_PRW, 0, NotSerialized)
+ {
+ Return (Package (0x02) {0x0E,0x04})
+ }
+ }
+ //
+ // System Wake up
+ //
+ Method(_WAK, 1, Serialized)
+ {
+ // Do nothing here
+ Return (0)
+ }
+
+ //
+ // System sleep down
+ //
+ Method (_PTS, 1, NotSerialized)
+ {
+ // Get ready for S3 sleep
+ if (Lequal(Arg0,3))
+ {
+ Store(0xffffffff,SMIS) // clear SMI status
+ Store(SMIE, Local0) // SMI Enable
+ Or(Local0,0x4,SMIE) // Generate SMI on sleep
+ }
+ }
+
+ //
+ // Determing PIC mode
+ //
+ Method(\_PIC, 1, NotSerialized)
+ {
+ Store(Arg0,\GPIC)
+ }
+
+ //
+ // System Bus
+ //
+ Scope(\_SB)
+ {
+ Device(PCI0)
+ {
+ Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root
Bridge
+
+ Name(_ADR,0x00000000) // Device (HI WORD)=0, Func
(LO WORD)=0
+ Method (_INI)
+ {
+ Store(LINUX, OSTP) // Set the default os is
Linux
+ If (CondRefOf (_OSI, local0))
+ {
+ //
+ //_OSI is supported, so it is WinXp or Win2003Server
+ //
+ If (\_OSI("Windows 2001"))
+ {
+ Store (WINDOWS_XP, OSTP)
+ }
+ If (\_OSI("Windows 2001 SP1"))
+ {
+ Store (WINDOWS_XP_SP1, OSTP)
+ }
+ If (\_OSI("Windows 2001 SP2"))
+ {
+ Store (WINDOWS_XP_SP2, OSTP)
+ }
+ If (\_OSI("Windows 2001.1"))
+ {
+ Store (WINDOWS_2003, OSTP)
+ }
+ If (\_OSI("Windows 2006"))
+ {
+ Store (WINDOWS_Vista, OSTP)
+ }
+ If (\_OSI("Windows 2009"))
+ {
+ Store (WINDOWS_WIN7, OSTP)
+ }
+ If (\_OSI("Windows 2012"))
+ {
+ Store (WINDOWS_WIN8, OSTP)
+ }
+ If (\_OSI("Windows 2013"))
+ {
+ Store (WINDOWS_WIN8_1, OSTP)
+ }
+ If (\_OSI("Linux"))
+ {
+ Store (LINUX, OSTP)
+ }
+ }
+ }
+
+ Include ("PciHostBridge.asi") // PCI0 Host bridge
+ Include ("QNC.asi") // QNC miscellaneous
+ Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices
+ Include ("QuarkSouthCluster.asi") // Quark South Cluster devices
+ Include ("QNCLpc.asi") // LPC bridge device
+ Include ("QNCApic.asi") // QNC I/O Apic device
+
+ }
+
+ //
+ // Include asi files for I2C and SPI onboard devices.
+ // Devices placed here instead of below relevant controllers.
+ // Hardware topology information is maintained by the
+ // ResourceSource arg to the I2CSerialBus/SPISerialBus macros
+ // within the device asi files.
+ //
+ Include ("Tpm.asi") // TPM device.
+ Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM
+ Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.
+ Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.
+ Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.
+ Include ("AD7298.asi") // Analog devices AD7298 ADC.
+ Include ("ADC108S102.asi") // TI ADC108S102 ADC.
+ Include ("GpioClient.asi") // Software device to expose GPIO
+ }
+}
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,55 @@
+/** @file
+QNC devices
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef QNC_ASI
+#define QNC_ASI
+
+Device(IOCM) // I/O controller miscellaneous
+{
+ Name(_HID,EISAID("PNP0C02")) // System board resources device node ID
+
+ Name(CRS, ResourceTemplate()
+ {
+
+ // PCIEXBAR memory range
+ Memory32Fixed(ReadOnly, 0, 0, FIX1)
+
+ // RCRB memory range
+ Memory32Fixed(ReadOnly, 0, 0, FIX2)
+
+ // Option ROM shadow memory range
+ Memory32Fixed(ReadOnly, 0x000C0000, 0x20000)
+
+ // BIOS ROM shadow memory range
+ Memory32Fixed(ReadOnly, 0x000E0000, 0x20000)
+
+ // BIOS Firmware just below 4GByte of memory 8MBytes
+ Memory32Fixed(ReadOnly, 0xFF800000, 0x800000)
+ }
+ )
+
+ Method (_CRS, 0, NotSerialized) {
+ CreateDWordField (CRS, ^FIX1._BAS, MBR0)
+ Store(\PEXB, MBR0)
+ CreateDWordField (CRS, ^FIX1._LEN, MBR1)
+ Store(\PEXS, MBR1)
+ CreateDWordField (CRS, ^FIX2._BAS, MBR2)
+ Store(\RCBB, MBR2)
+ CreateDWordField (CRS, ^FIX2._LEN, MBR3)
+ Store(\RCBS, MBR3)
+ Return (CRS)
+ }
+}
+#endif
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,38 @@
+/** @file
+QNC I/O Apic devices
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef QNC_APIC_ASI
+#define QNC_APIC_ASI
+
+Device(APIC)
+{
+ Name(_HID,EISAID("PNP0003")) // APIC resources
+
+ Name(CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC
+ }
+ )
+
+ Method (_CRS, 0, NotSerialized) {
+ CreateDWordField (CRS, ^FIX1._BAS, MBR0)
+ Store(\APCB, MBR0)
+ CreateDWordField (CRS, ^FIX1._LEN, MBR1)
+ Store(\APCS, MBR1)
+ Return (CRS)
+ }
+}
+
+#endif
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,29 @@
+/** @file
+Lpc devices and control methods
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef QNC_LPC_ASI
+#define QNC_LPC_ASI
+
+Device(LPC)
+{
+ Name(_ADR,0x001f0000) // Device (HI WORD)=31, Func (LO WORD)=0
+
+ Include ("PciIrq.asi") // PCI routing control methods
+ Include ("LpcDev.asi") // Static Lpc device resource declaration
+}
+
+
+#endif
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi
2015-12-15 19:23:57 UTC (rev 19287)
@@ -0,0 +1,116 @@
+/** @file
+Quark South Cluster Devices.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef QuarkSouthCluster_asi
+#define QuarkSouthCluster_asi
+
+Device (SDIO) // SDIO [Bus 0, Device 20, Function 0]
+{
+ Name(_ADR,0x00140000) // Device (HI WORD)=20, Func (LO WORD)=0
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (URT0) // UART0 [Bus 0, Device 20, Function 1]
+{
+ Name(_ADR,0x00140001) // Device (HI WORD)=20, Func (LO WORD)=1
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (USBD) // USB Device [Bus 0, Device 20, Function 2]
+{
+ Name(_ADR,0x00140002) // Device (HI WORD)=20, Func (LO WORD)=2
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (EHCI) // EHCI [Bus 0, Device 20, Function 3]
+{
+ Name(_ADR,0x00140003) // Device (HI WORD)=20, Func (LO WORD)=3
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (OHCI) // OHCI [Bus 0, Device 20, Function 4]
+{
+ Name(_ADR,0x00140004) // Device (HI WORD)=20, Func (LO WORD)=4
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (URT1) // UART1 [Bus 0, Device 20, Function 5]
+{
+ Name(_ADR,0x00140005) // Device (HI WORD)=20, Func (LO WORD)=5
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (ENT0) // Ethernet0 [Bus 0, Device 20, Function 6]
+{
+ Name(_ADR,0x00140006) // Device (HI WORD)=20, Func (LO WORD)=6
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (ENT1) // Ethernet1 [Bus 0, Device 20, Function 7]
+{
+ Name(_ADR,0x00140007) // Device (HI WORD)=20, Func (LO WORD)=7
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (SPI0) // SPI0 [Bus 0, Device 21, Function 0]
+{
+ Name(_ADR,0x00150000) // Device (HI WORD)=21, Func (LO WORD)=0
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (SPI1) // SPI1 [Bus 0, Device 21, Function 1]
+{
+ Name(_ADR,0x00150001) // Device (HI WORD)=21, Func (LO WORD)=1
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+}
+
+Device (GIP0) // I2C/GPIO [Bus 0, Device 21, Function 2]
+{
+ Name(_ADR,0x00150002) // Device (HI WORD)=21, Func (LO WORD)=2
+ Name(_STA,0xF) // Enabled, do Display
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
+
+ Device(GPO_) // GPIO Virtual Child Device- for BAR0 resources
+ {
+ Name(_ADR, 0)
+ Name(_STA, 0xf)
+ Name(_PRW, Package(0x2)
+ {
+ 0xf,
+ 0x3
+ })
+ }
+ Device(I2C_) // I2C Controller Virtual Child Device- for BAR1 resources
+ {
+ Name(_ADR, 1)
+ Name(_STA, 0xf)
+ Name(_PRW, Package(0x2)
+ {
+ 0xf,
+ 0x3
+ })
+ }
+}
+#endif
Added: trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi
===================================================================
--- trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi
(rev 0)
+++ trunk/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi 2015-12-15
19:23:57 UTC (rev 19287)
@@ -0,0 +1,51 @@
+/** @file
+
+The Infineon SLB9645 TPM ACPI definition block.
+Provides TPM device info. and TPM presence check only.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device (TPM)
+{
+ //
+ // Define _HID as Infineon TPM Device, _CID as "PNP0C31" (defined in
+ // "Secure Startup-FVE and TPM Admin BIOS and Platform Requirements").
+ //
+ Name(_HID ,EISAID("INT3493"))
+ Name(_CID, EISAID("PNP0C31"))
+
+ //
+ // Readable name of this device.
+ //
+ Name (_STR, Unicode ("Infineon TPM 1.2 Device (SLB9645TT1.2)"))
+
+ //
+ // Return the resource consumed by TPM device.
+ //
+ Name (_CRS, ResourceTemplate () {
+ I2cSerialBus (0x20, ControllerInitiated, 0x00061A80, AddressingMode7Bit,
"\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer,,)
+ })
+
+ //
+ // Check if TPM present.
+ //
+ Method (_STA, 0)
+ {
+ if (LEqual (TPMP, 0))
+ {
@@ Diff output truncated at 100000 characters. @@
------------------------------------------------------------------------------
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