Branch: refs/heads/master
Home: https://github.com/tianocore/edk2
Commit: b5f20eca8a08c2921b4844e736f97d3450144ed5
https://github.com/tianocore/edk2/commit/b5f20eca8a08c2921b4844e736f97d3450144ed5
Author: Sheng Wei <[email protected]>
Date: 2023-12-07 (Thu, 07 Dec 2023)
Changed paths:
A UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc
Log Message:
-----------
UefiCpuPkg: Add macro definitions for CET feature for NASM files.
Signed-off-by: Sheng Wei <[email protected]>
Cc: Eric Dong <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Wu Jiaxin <[email protected]>
Cc: Tan Dun <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Commit: 04d47a9bf0068b88453154e2028a26b626c04147
https://github.com/tianocore/edk2/commit/04d47a9bf0068b88453154e2028a26b626c04147
Author: Sheng Wei <[email protected]>
Date: 2023-12-07 (Thu, 07 Dec 2023)
Changed paths:
M UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
M UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
Log Message:
-----------
UefiCpuPkg: Use macro CR4_CET_BIT to replace hard code value in Cet.nasm.
Signed-off-by: Sheng Wei <[email protected]>
Cc: Eric Dong <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Wu Jiaxin <[email protected]>
Cc: Tan Dun <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Commit: 3018685da8a46d1cfb5d7bdfcded16940709d9da
https://github.com/tianocore/edk2/commit/3018685da8a46d1cfb5d7bdfcded16940709d9da
Author: Sheng Wei <[email protected]>
Date: 2023-12-07 (Thu, 07 Dec 2023)
Changed paths:
M UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
M UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
Log Message:
-----------
UefiCpuPkg: Use CET macro definitions in Cet.inc for SmiEntry.nasm files.
Signed-off-by: Sheng Wei <[email protected]>
Cc: Eric Dong <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Wu Jiaxin <[email protected]>
Cc: Tan Dun <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Commit: fd1dd8568c78c594540990eaa4fbe37fdd3b1839
https://github.com/tianocore/edk2/commit/fd1dd8568c78c594540990eaa4fbe37fdd3b1839
Author: Sheng Wei <[email protected]>
Date: 2023-12-07 (Thu, 07 Dec 2023)
Changed paths:
M UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
M UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
Log Message:
-----------
UefiCpuPkg: Only change CR4.CET bit for enable and disable CET.
Signed-off-by: Sheng Wei <[email protected]>
Cc: Eric Dong <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Wu Jiaxin <[email protected]>
Cc: Tan Dun <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Commit: 553dfb0f57ae8a666938873cf836a33549568c87
https://github.com/tianocore/edk2/commit/553dfb0f57ae8a666938873cf836a33549568c87
Author: Sheng Wei <[email protected]>
Date: 2023-12-07 (Thu, 07 Dec 2023)
Changed paths:
M UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
M UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
Log Message:
-----------
UefiCpuPkg: Backup and Restore MSR IA32_U_CET in SMI handler.
OS may enable CET-IBT feature by set MSR IA32_U_CET.bit2.
If IA32_U_CET.bit2 is set, CPU is in WAIT_FOR_ENDBRANCH state and
the next assemble code is not ENDBR, it will trigger #CP exception
when set CR4.CET bit.
SMI handler needs to backup MSR IA32_U_CET and clear MSR IA32_U_CET
before set CR4.CET bit,
And SMI handler needs to restore MSR IA32_U_CET when exit SMI handler.
Signed-off-by: Sheng Wei <[email protected]>
Cc: Eric Dong <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Laszlo Ersek <[email protected]>
Cc: Wu Jiaxin <[email protected]>
Cc: Tan Dun <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Compare: https://github.com/tianocore/edk2/compare/ff4c49a5ee38...553dfb0f57ae
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