Some updates to SCR can cause a problem which manifests as an undefined opcode 
exception.
This may be when a speculative secure instruction fetch happens after the NS 
bit is set.
An isb is required to make the register change take effect fully.

Contributed-under: Tianocore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <[email protected]>
Reviewed-by: Sami Mujawar <[email protected]>
---
diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S 
b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
index 28db98b..50faef4 100644
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
@@ -184,6 +184,7 @@ ASM_PFX(ArmWriteCptr):

 ASM_PFX(ArmWriteScr):
   msr     scr_el3, x0            // Secure configuration register EL3
+  isb
   ret

 ASM_PFX(ArmWriteMVBar):
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S 
b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index 43842f3..ffeaed3 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -153,6 +153,7 @@ ASM_PFX(ArmReadScr):

 ASM_PFX(ArmWriteScr):
   mcr     p15, 0, r0, c1, c1, 0
+  isb
   bx      lr

 ASM_PFX(ArmReadHVBar):
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm 
b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index 8864c16..15bfb6e 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -153,6 +153,7 @@ ArmReadScr

 ArmWriteScr
   mcr     p15, 0, r0, c1, c1, 0
+  isb
   bx      lr

 ArmReadHVBar



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