On 25 August 2015 at 17:59, Evan Lloyd <[email protected]> wrote: > Some updates to SCR can cause a problem which manifests as an undefined > opcode exception. > This may be when a speculative secure instruction fetch happens after the NS > bit is set. > An isb is required to make the register change take effect fully. > > Contributed-under: Tianocore Contribution Agreement 1.0 > Signed-off-by: Evan Lloyd <[email protected]> > Reviewed-by: Sami Mujawar <[email protected]>
Reviewed-by: Ard Biesheuvel <[email protected]> > --- > diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S > b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S > index 28db98b..50faef4 100644 > --- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S > @@ -184,6 +184,7 @@ ASM_PFX(ArmWriteCptr): > > ASM_PFX(ArmWriteScr): > msr scr_el3, x0 // Secure configuration register EL3 > + isb > ret > > ASM_PFX(ArmWriteMVBar): > diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S > b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S > index 43842f3..ffeaed3 100644 > --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S > @@ -153,6 +153,7 @@ ASM_PFX(ArmReadScr): > > ASM_PFX(ArmWriteScr): > mcr p15, 0, r0, c1, c1, 0 > + isb > bx lr > > ASM_PFX(ArmReadHVBar): > diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm > b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm > index 8864c16..15bfb6e 100644 > --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm > +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm > @@ -153,6 +153,7 @@ ArmReadScr > > ArmWriteScr > mcr p15, 0, r0, c1, c1, 0 > + isb > bx lr > > ArmReadHVBar > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > _______________________________________________ > edk2-devel mailing list > [email protected] > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
