From: Paolo Bonzini <[email protected]> According to Intel this is invalid. Go back to 32-bit protected mode and clear EFER.LME before executing RSM.
Cc: Michael Kinney <[email protected]> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paolo Bonzini <[email protected]> --- Notes: v3: - New in v3, but included only for completeness here. This is a correction from Paolo for Mike's series "[edk2] [PATCH 0/7] UefiCpuPkg: Add CPU SMM and SecCore". UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 13 +++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 13 +++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.S | 13 +++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm | 13 +++++++++++++ 4 files changed, 52 insertions(+) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S index 8315593..0f1cab6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -212,6 +212,19 @@ L1: .byte 0x48, 0x89, 0x0d # mov [rip + disp32], rcx .long SSM_DR6 - (. + 4 - _SmiEntryPoint + 0x8000) L2: + + pushq $PROTECT_MODE_CS + pushq $L3 + lretq +L3: + movq %cr0, %rbx + btrl $31, %ebx + movq %rbx, %cr0 + movl $0xc0000080, %ecx + rdmsr + andb $0xfe,%ah + wrmsr + rsm ASM_PFX(gcSmiHandlerSize): .word . - _SmiEntryPoint diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm index a1a7d3e..99eb403 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -214,6 +214,19 @@ _SmiHandler: DB 48h, 89h, 0dh ; mov [rip + disp32], rcx DD SSM_DR6 - ($ + 4 - _SmiEntryPoint + 8000h) @2: + + push PROTECT_MODE_CS + push @3 + retfq +@3: + mov rbx, cr0 + btr ebx, 31 + mov cr0, rbx + mov ecx, 0c0000080h + rdmsr + and ah, 0feh + wrmsr + rsm gcSmiHandlerSize DW $ - _SmiEntryPoint diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.S index 5ace1a6..fc7c2f9 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.S @@ -32,6 +32,7 @@ ASM_GLOBAL ASM_PFX(mSmmRelocationOriginalAddressPtr32) ASM_GLOBAL ASM_PFX(gSmmInitStack) ASM_GLOBAL ASM_PFX(gcSmiInitGdtr) +.equ PROTECT_MODE_CS, 0x08 .text @@ -89,6 +90,18 @@ ASM_PFX(gSmmInitStack): .space 8 movdqa 0x40(%rsp), %xmm4 movdqa 0x50(%rsp), %xmm5 + pushq $PROTECT_MODE_CS # push 32-bit CS + pushq $L3 + lretq +L3: + movq %cr0, %rbx # get out of long mode + btrl $31, %ebx + movq %rbx, %cr0 + movl $0xc0000080, %ecx + rdmsr + andb $0xfe,%ah + wrmsr + rsm ASM_PFX(gcSmmInitTemplate): diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm index 25a0447..68540a6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm @@ -32,6 +32,8 @@ EXTERNDEF mSmmRelocationOriginalAddressPtr32:DWORD EXTERNDEF gSmmInitStack:QWORD EXTERNDEF gcSmiInitGdtr:FWORD +PROTECT_MODE_CS EQU 08h + .code gcSmiInitGdtr LABEL FWORD @@ -88,6 +90,17 @@ gSmmInitStack DQ ? movdqa xmm4, [rsp + 40h] movdqa xmm5, [rsp + 50h] + push PROTECT_MODE_CS + push @3 + retfq +@3: + mov rbx, cr0 + btr ebx, 31 + mov cr0, rbx + mov ecx, 0c0000080h + rdmsr + and ah, 0feh + wrmsr rsm SmmStartup ENDP -- 1.8.3.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
