On 3 November 2015 at 14:51, Cohen, Eugene <eug...@hp.com> wrote: > Please don't remove this functionality. At times we do want to use this > library to turn off the cache in preparation for going to another environment > (say, loading an OS) and this is useful. >
Note that this is not about turning off the caches. As Mark points out, the set/way operations are not suitable for ensuring that the OS boot image has made it all the way to memory, and that it will be visible to the CPU with the MMU off. The cache maintenance by VA operations do offer those guarantees, so the architecturally sound method of achieving that is to clean the region(s) you care about by VA before disabling the MMU. Under virtualization, these issues are a bit more prominent, and I have had to add by-VA cache maintenance on several occasions to fix actual problems. Note that this patch does not remove any of the functionality. It just changes the CacheMaintenanceLib implementation so that this functionality is not exported to generic code. If any non-ARM specific code in the tree requires the ability to clean and/or invalidate the whole data cache, it is making incorrect assumptions about the platform that it runs on. Regards, Ard. > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Ard > Biesheuvel > Sent: Tuesday, November 03, 2015 3:17 AM > To: edk2-devel@lists.01.org; leif.lindh...@linaro.org; mark.rutl...@arm.com > Cc: ler...@redhat.com; Ard Biesheuvel <ard.biesheu...@linaro.org> > Subject: [edk2] [PATCH 08/10] ArmCacheMaintenanceLib: disallow whole D-cache > maintenance operations > > The ARM architecture provides no reliable way to clean or invalidate the > entire data cache at runtime. The reason is that such maintenance requires > the use of set/way maintenance operations, which are suitable only for the > kind of maintenance that is carried out when the cache is taken offline > entirely. > > So ASSERT () when any of the CacheMaintenanceLib whole data cache routines > are invoked rather than pretending we can do anything meaningful here. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> > --- > ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > index 175d29496c32..8cc1990b3266 100644 > --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c > @@ -14,6 +14,7 @@ > **/ > #include <Base.h> > #include <Library/ArmLib.h> > +#include <Library/DebugLib.h> > #include <Library/PcdLib.h> > > VOID > @@ -44,7 +45,6 @@ InvalidateInstructionCache ( > VOID > ) > { > - ArmCleanDataCache(); > ArmInvalidateInstructionCache(); > } > > @@ -54,7 +54,7 @@ InvalidateDataCache ( > VOID > ) > { > - ArmInvalidateDataCache(); > + ASSERT (FALSE); > } > > VOID * > @@ -76,7 +76,7 @@ WriteBackInvalidateDataCache ( > VOID > ) > { > - ArmCleanInvalidateDataCache(); > + ASSERT (FALSE); > } > > VOID * > @@ -96,7 +96,7 @@ WriteBackDataCache ( > VOID > ) > { > - ArmCleanDataCache(); > + ASSERT (FALSE); > } > > VOID * > -- > 1.9.1 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
