> On Nov 4, 2015, at 7:41 AM, Mark Rutland <[email protected]> wrote: > > On Wed, Nov 04, 2015 at 04:24:20PM +0100, Laszlo Ersek wrote: >> On 11/04/15 16:19, Ard Biesheuvel wrote: > > [...] > >>> The problem remains that VA and set/way ops are completely different >>> things. Each by-VA operation handles all copies of the same cacheline >>> throughout the cache hierarchy at once. The set/way ops, on the other >>> hand, traverse each cache level in turn, leaving a time window between >>> the completion of the L1 maintenance and the completion of the L2 >>> maintenance where speculative accesses resulting in L1 misses are >>> happily served from the L2 and allocated in L1 -- unless your MMU and >>> I-cache are off. This means the logic that promotes from VA to set/way >>> ops should take MMU and I-cache state into account as well, and I am >>> not sure you would want to go there. >> >> Thanks for this great summary. >> >> So, why doesn't ARM provide instructions for flushing / invalidating the >> complete cache? Just curious. > > I don't have a an official answer, but there are several factors that > spring to mind. > > Because of system-level coherency, dirty cacheline migration, and so on, > performing an operation on the "complete cache" would mean performing > the operation on every cache in the system (e.g. CPUs, system L3, > coherent devices, etc). That's an enormous amount of data and associated > state to keep track of, and it could take an extremely long time for > such maintenance to complete. > > It's almost never necessary to clean or invalidate the entire cache > hierarchy in a system.
Well some how those almost cases always seem to show up in firmware :). > In practically every scenario, maintenance by VA > can be used to provide the necessary guarantees, so the complexity of > implementing the above can be avoided. > If we step back and think about it a little.... We have the generic edk2 cache maintenance, and the only one that comes to mind is flushing the instruction cache after PE/COFF images are loaded. Then there is the cache init/maintenance required by the CPU architecture so setting up MMUs, (MTRRs on x86), changing system mappings, and for ARM DMA. So it would be good to make the common cases clear. For example the Cache Operations in the MdePkg started out as the set of operations you need to do generically for an x86 or Itanium processor. Thanks, Andrew Fish > Thanks, > Mark. > _______________________________________________ > edk2-devel mailing list > [email protected] > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
