[edk2] [PATCH v3 3/3] ArmPkg/ArmV7Mmu: introduce feature PCD to map normal memory non-shareable

[Ard Biesheuvel]

Even though mapping normal memory (inner) shareable is usually the
correct choice on coherent systems, it may be desirable in some cases
to use non-shareable mappings for normal memory, e.g., when hardware
managed coherency is not required and the memory system is not fully
configured yet. So introduce a PCD PcdNormalMemoryNonshareableOverride
that makes cacheable mappings of normal memory non-shareable.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
---
 ArmPkg/ArmPkg.dec                             |  6 ++++++
 ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf      |  3 +++
 ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf |  3 +++
 ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c        | 12 ++++++++++++
 4 files changed, 24 insertions(+)

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 46e9894d3f56..ff4531e44106 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -73,6 +73,12 @@ [PcdsFeatureFlag.common]
   # Define if the GICv3 controller should use the GICv2 legacy
   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
 
+[PcdsFeatureFlag.ARM]
+  # Whether to map normal memory as non-shareable. FALSE is the safe choice, 
but
+  # TRUE may be appropriate to fix performance problems if you don't care about
+  # hardware coherency (i.e., no virtualization or cache coherent DMA)
+  
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf 
b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
index 01bdfb699656..d56851a1409b 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
@@ -48,3 +48,6 @@ [LibraryClasses]
 
 [Protocols]
   gEfiCpuArchProtocolGuid
+
+[FeaturePcd.ARM]
+  gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf 
b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
index ac081068db28..6eaf350c7b9d 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
@@ -48,3 +48,6 @@ [LibraryClasses]
 
 [Protocols]
   gEfiCpuArchProtocolGuid
+
+[FeaturePcd.ARM]
+  gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c 
b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index 2bfbd9172a74..6e16e3a7d984 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -80,6 +80,10 @@ PopulateLevel2PageTable (
       break;
   }
 
+  if (FeaturePcdGet(PcdNormalMemoryNonshareableOverride)) {
+    PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
+  }
+
   // Check if the Section Entry has already been populated. Otherwise attach a
   // Level 2 Translation Table to it
   if (*SectionEntry != 0) {
@@ -178,6 +182,10 @@ FillTranslationTable (
       break;
   }
 
+  if (FeaturePcdGet(PcdNormalMemoryNonshareableOverride)) {
+    Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
+  }
+
   // Get the first section entry for this mapping
   SectionEntry    = 
TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, 
MemoryRegion->VirtualBase);
 
@@ -265,6 +273,10 @@ ArmConfigureMmu (
     return RETURN_UNSUPPORTED;
   }
 
+  if (FeaturePcdGet(PcdNormalMemoryNonshareableOverride)) {
+    TTBRAttributes &= ~TTBR_SHAREABLE;
+  }
+
   ArmCleanInvalidateDataCache ();
   ArmInvalidateInstructionCache ();
 
-- 
1.9.1

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