On Tue, Nov 17, 2015 at 03:59:13PM +0100, Ard Biesheuvel wrote: > To align with the way normal cacheable memory is mapped, set the > shareable bit for cached accesses performed by the page table walker. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]> > --- > ArmPkg/Include/Chipset/ArmV7Mmu.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h > b/ArmPkg/Include/Chipset/ArmV7Mmu.h > index 4cd35bd0e36e..2374b0acd54e 100644 > --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h > +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h > @@ -29,10 +29,10 @@ > #define TTBR_RGN_INNER_WRITE_THROUGH BIT0 > #define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6) > > -#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | > TTBR_RGN_INNER_WRITE_THROUGH ) > -#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC > | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC ) > +#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | > TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE) > +#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC > | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE) > #define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | > TTBR_RGN_INNER_NON_CACHEABLE ) > -#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | > TTBR_RGN_INNER_WRITE_BACK_ALLOC ) > +#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | > TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE) > > > #define TRANSLATION_TABLE_SECTION_COUNT 4096 > -- > 1.9.1 > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
