Current implementation only supports legacy region of 440 chip. When QEMU is launched in Q35 mode using CSM enabled OVMF image, LegacyBios driver fails to start due to the legacy region [0xC0000, 0xFFFFF] cannot be written.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <[email protected]> Cc: Justen Jordan <[email protected]> Cc: Laszlo Ersek <[email protected]> --- OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c | 55 +++++++++++++++++++++++--------- OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h | 27 ++++++++++------ 2 files changed, 58 insertions(+), 24 deletions(-) diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c index 44d340b..06330fd 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c @@ -1,7 +1,7 @@ /** @file Legacy Region Support - Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -50,22 +50,40 @@ STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = { {0xF0000, SIZE_64KB, FALSE, FALSE} }; -STATIC PAM_REGISTER_VALUE mRegisterValues[] = { - {REG_PAM1_OFFSET, 0x01, 0x02}, - {REG_PAM1_OFFSET, 0x10, 0x20}, - {REG_PAM2_OFFSET, 0x01, 0x02}, - {REG_PAM2_OFFSET, 0x10, 0x20}, - {REG_PAM3_OFFSET, 0x01, 0x02}, - {REG_PAM3_OFFSET, 0x10, 0x20}, - {REG_PAM4_OFFSET, 0x01, 0x02}, - {REG_PAM4_OFFSET, 0x10, 0x20}, - {REG_PAM5_OFFSET, 0x01, 0x02}, - {REG_PAM5_OFFSET, 0x10, 0x20}, - {REG_PAM6_OFFSET, 0x01, 0x02}, - {REG_PAM6_OFFSET, 0x10, 0x20}, - {REG_PAM0_OFFSET, 0x10, 0x20} +STATIC PAM_REGISTER_VALUE mRegisterValues440[] = { + {REG_PAM1_OFFSET_440, 0x01, 0x02}, + {REG_PAM1_OFFSET_440, 0x10, 0x20}, + {REG_PAM2_OFFSET_440, 0x01, 0x02}, + {REG_PAM2_OFFSET_440, 0x10, 0x20}, + {REG_PAM3_OFFSET_440, 0x01, 0x02}, + {REG_PAM3_OFFSET_440, 0x10, 0x20}, + {REG_PAM4_OFFSET_440, 0x01, 0x02}, + {REG_PAM4_OFFSET_440, 0x10, 0x20}, + {REG_PAM5_OFFSET_440, 0x01, 0x02}, + {REG_PAM5_OFFSET_440, 0x10, 0x20}, + {REG_PAM6_OFFSET_440, 0x01, 0x02}, + {REG_PAM6_OFFSET_440, 0x10, 0x20}, + {REG_PAM0_OFFSET_440, 0x10, 0x20} }; +STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] = { + {REG_PAM1_OFFSET_Q35, 0x01, 0x02}, + {REG_PAM1_OFFSET_Q35, 0x10, 0x20}, + {REG_PAM2_OFFSET_Q35, 0x01, 0x02}, + {REG_PAM2_OFFSET_Q35, 0x10, 0x20}, + {REG_PAM3_OFFSET_Q35, 0x01, 0x02}, + {REG_PAM3_OFFSET_Q35, 0x10, 0x20}, + {REG_PAM4_OFFSET_Q35, 0x01, 0x02}, + {REG_PAM4_OFFSET_Q35, 0x10, 0x20}, + {REG_PAM5_OFFSET_Q35, 0x01, 0x02}, + {REG_PAM5_OFFSET_Q35, 0x10, 0x20}, + {REG_PAM6_OFFSET_Q35, 0x01, 0x02}, + {REG_PAM6_OFFSET_Q35, 0x10, 0x20}, + {REG_PAM0_OFFSET_Q35, 0x10, 0x20} +}; + +STATIC PAM_REGISTER_VALUE *mRegisterValues; + // // Handle used to install the Legacy Region Protocol // @@ -451,6 +469,13 @@ LegacyRegionInit ( { EFI_STATUS Status; + if (PciRead16 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, PCI_DEVICE_ID_OFFSET)) + == PAM_DEVICE_ID_Q35) { + mRegisterValues = mRegisterValuesQ35; + } else { + mRegisterValues = mRegisterValues440; + } + // // Install the Legacy Region Protocol on a new handle // diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h index 805df86..39e2b6b 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h @@ -1,7 +1,7 @@ /** @file Legacy Region Support - Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -31,14 +31,23 @@ #define PAM_PCI_BUS 0 #define PAM_PCI_DEV 0 #define PAM_PCI_FUNC 0 - -#define REG_PAM0_OFFSET 0x59 // Programmable Attribute Map 0 -#define REG_PAM1_OFFSET 0x5a // Programmable Attribute Map 1 -#define REG_PAM2_OFFSET 0x5b // Programmable Attribute Map 2 -#define REG_PAM3_OFFSET 0x5c // Programmable Attribute Map 3 -#define REG_PAM4_OFFSET 0x5d // Programmable Attribute Map 4 -#define REG_PAM5_OFFSET 0x5e // Programmable Attribute Map 5 -#define REG_PAM6_OFFSET 0x5f // Programmable Attribute Map 6 +#define PAM_DEVICE_ID_Q35 0x29C0 + +#define REG_PAM0_OFFSET_440 0x59 // Programmable Attribute Map 0 +#define REG_PAM1_OFFSET_440 0x5a // Programmable Attribute Map 1 +#define REG_PAM2_OFFSET_440 0x5b // Programmable Attribute Map 2 +#define REG_PAM3_OFFSET_440 0x5c // Programmable Attribute Map 3 +#define REG_PAM4_OFFSET_440 0x5d // Programmable Attribute Map 4 +#define REG_PAM5_OFFSET_440 0x5e // Programmable Attribute Map 5 +#define REG_PAM6_OFFSET_440 0x5f // Programmable Attribute Map 6 + +#define REG_PAM0_OFFSET_Q35 0x90 // Programmable Attribute Map 0 +#define REG_PAM1_OFFSET_Q35 0x91 // Programmable Attribute Map 1 +#define REG_PAM2_OFFSET_Q35 0x92 // Programmable Attribute Map 2 +#define REG_PAM3_OFFSET_Q35 0x93 // Programmable Attribute Map 3 +#define REG_PAM4_OFFSET_Q35 0x94 // Programmable Attribute Map 4 +#define REG_PAM5_OFFSET_Q35 0x95 // Programmable Attribute Map 5 +#define REG_PAM6_OFFSET_Q35 0x96 // Programmable Attribute Map 6 #define PAM_BASE_ADDRESS 0xc0000 #define PAM_LIMIT_ADDRESS BASE_1MB -- 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
