Hi Laszlo,

> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Friday, October 14, 2016 5:37 PM
> 
> On 10/14/16 11:33, Bhupesh Sharma wrote:
> > Various IPs on NXP/FSL SoCs having ARM64 cores have big-endian MMIO
> > interfaces.
> >
> > This implies that a byte-swap operation is needed to read/write such
> > BE MMIO registers from the LE ARM64 cores.
> >
> > This patch adds the support for the same.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sha...@nxp.com>
> > ---
> >  MdePkg/Include/Library/IoLib.h               | 364
> ++++++++++++++++++++
> >  MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c | 479
> > +++++++++++++++++++++++++++
> >  2 files changed, 843 insertions(+)
> 
> I think this is both overkill and incomplete, at the same time :)
> 
> - Incomplete because only one IoLib instance gets the implementation.

Agree, but do we have an example of similar BE MMIO IPs on other
Architectures/soc? I was only aware of NXP/FSL having such MMIO
interfaces as the IPs have been reused from PPC SoC, which used
to have a BE core and hence did not require a SwapByte.
 
> - Overkill because you can easily use the SwapBytes16, SwapBytes32,
> SwapBytes64 functions -- also from BaseLib --, for transforming
> MmioWrite arguments and MmioRead results.
> 

Yes, but that means at every IP driver needs to especially carry such
arguments and transform the results. That might be an overkill.

We already have similar implementations MMIO implementations in Linux for e.g.
http://lxr.free-electrons.com/source/include/asm-generic/io.h#L642

Regards,
Bhupesh
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