On 16 May 2017 at 03:56, Sergey Temerkhanov <[email protected]> wrote: > These registers are reserved for PPIs and unimplemented on > some architectures >
What do you mean by 'architectures'? Could you elaborate on which SoC needs this? > Signed-off-by: Sergey Temerkhanov <[email protected]> > --- > ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > index 8af97a9..dc6b896 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > @@ -257,7 +257,7 @@ GicV3DxeInitialize ( > MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE); > } > > - for (Index = 0; Index < mGicNumInterrupts; Index++) { > + for (Index = 32; Index < mGicNumInterrupts; Index++) { > GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); > > // Set Priority > -- > 2.7.4 > > _______________________________________________ > edk2-devel mailing list > [email protected] > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
