On Wed, Oct 25, 2017 at 06:59:29PM +0100, Ard Biesheuvel wrote: > Having two distinct root complexes is not supported by the standard > set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one > of the latter specifically for this platform (and forget about the > others). > > This also allows us to implement the Synopsys Designware PCIe specific > workaround for PCI config space accesses to devices 1 and up on bus 0. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]> / Leif _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
