On Fri, Nov 10, 2017 at 02:21:19PM +0000, Ard Biesheuvel wrote:
> Describe the SynQuacer SoC's eMMC controller in DT so the OS can
> attach to it.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
So, slightly obnoxious, but...
Since this is the .dtsi for the SoC as a whole, is there any
convenient way for us to selectively exclude this bit when building?
Some platforms may not use this, and some may chose not to expose it
to the OS.
/
Leif
> ---
> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 26
> ++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> index e72db377bc39..cf06acc75297 100644
> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> @@ -532,4 +532,30 @@
> #interrupt-cells = <3>;
> socionext,spi-base = <112>;
> };
> +
> + clk_alw_b_0: bclk200 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + clock-output-names = "sd_bclk";
> + };
> +
> + clk_alw_c_0: sd4clk800 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <800000000>;
> + clock-output-names = "sd_sd4clk";
> + };
> +
> + sdhci@52300000 {
> + compatible = "socionext,synquacer-sdhci",
> "fujitsu,mb86s70-sdhci-3.0";
> + reg = <0 0x52300000 0x0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + fujitsu,cmd-dat-delay-select;
> + clocks = <&clk_alw_c_0 &clk_alw_b_0>;
> + clock-names = "core", "iface";
> + };
> };
> --
> 2.11.0
>
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