In order to accommodate the EVB, whose PCIe RC #0 should not be touched by software if no card is inserted, add a PCD that tells the PCIe driver code which RCs should be initialized and exposed to the PCI host bridge driver.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <[email protected]> --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 19 ++++++++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 3 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 30 +++++++++----------- Silicon/Socionext/SynQuacer/SynQuacer.dec | 4 +++ 4 files changed, 36 insertions(+), 20 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 42cdce24b2c4..596862baf469 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -92,7 +92,7 @@ CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { #define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM #endif -STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = { +PCI_ROOT_BRIDGE mPciRootBridges[] = { { 0, // Segment 0, // Supports @@ -149,9 +149,20 @@ PciHostBridgeGetRootBridges ( OUT UINTN *Count ) { - *Count = ARRAY_SIZE (mPciRootBridges); - - return mPciRootBridges; + switch (PcdGet8 (PcdPcieEnableMask)) { + default: + ASSERT (FALSE); + case 0x0: + *Count = 0; + return NULL; + case 0x1: + case 0x2: + *Count = 1; + return &mPciRootBridges[PcdGet8 (PcdPcieEnableMask) - 1]; + case 0x3: + *Count = ARRAY_SIZE (mPciRootBridges); + return mPciRootBridges; + } } /** diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 5d87727c73ba..27fcba034418 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf @@ -49,3 +49,6 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdPciIoTranslation + +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 3da94945f96a..bea40e3dcfe8 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -120,6 +120,8 @@ #define MISC_CONTROL_1_OFF 0x8BC #define DBI_RO_WR_EN BIT0 +extern PCI_ROOT_BRIDGE mPciRootBridges[]; + STATIC VOID ConfigureWindow ( @@ -390,18 +392,12 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - PCI_ROOT_BRIDGE *RootBridges; - UINTN Count; UINTN Idx; - RootBridges = PciHostBridgeGetRootBridges (&Count); - ASSERT (Count == ARRAY_SIZE(mBaseAddresses)); - if (Count != ARRAY_SIZE(mBaseAddresses)) { - return EFI_INVALID_PARAMETER; - } - - for (Idx = 0; Idx < Count; Idx++) { - PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + } } // @@ -412,12 +408,14 @@ SynQuacerPciHostBridgeLibConstructor ( // gBS->Stall (150 * 1000); - for (Idx = 0; Idx < Count; Idx++) { - PciInitControllerPost (mBaseAddresses[Idx].ExsBase, - mBaseAddresses[Idx].DbiBase, - mBaseAddresses[Idx].ConfigBase, - mBaseAddresses[Idx].IoMemBase, - &RootBridges[Idx]); + for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, + mBaseAddresses[Idx].DbiBase, + mBaseAddresses[Idx].ConfigBase, + mBaseAddresses[Idx].IoMemBase, + &mPciRootBridges[Idx]); + } } return EFI_SUCCESS; diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 02dd6ac417f9..2e18cb33346d 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -38,3 +38,7 @@ [PcdsFixedAtBuild] gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004 gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005 + +[PcdsPatchableInModule, PcdsDynamic] + # Enable both RC #0 and RC #1 by default + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007 -- 2.11.0 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
