Suggested subject tweak: Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the OS -> Silicon/Socionext/SynQuacer: add UART #0 node to DT
with that: Reviewed-by: Leif Lindholm <[email protected]> On Tue, Dec 12, 2017 at 10:38:06AM +0000, Ard Biesheuvel wrote: > From: Masahisa KOJIMA <[email protected]> > > In order to be able to use UART #0 on the DeveloperBox's 96boards low > speed connector, expose it to the OS by adding a node to the device > tree. This requires a CM3 firmware build that makes the SCP detach > from the serial port after boot. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Masahisa KOJIMA <[email protected]> > Signed-off-by: Ard Biesheuvel <[email protected]> > --- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index c9fee5d1f350..37a3981f0360 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -440,6 +440,15 @@ > clock-names = "uartclk", "apb_pclk"; > }; > > + fuart: fuart@51040000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x51040000 0x0 0x1000>; > + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <62500000>; > + reg-io-width = <4>; > + reg-shift = <2>; > + }; > + > clk_netsec: refclk125mhz { > compatible = "fixed-clock"; > clock-frequency = <125000000>; > -- > 2.11.0 > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
