On 02/21/18 16:46, Leif Lindholm wrote:
> Apologies for dropping the ball on this series during my sabbatical.
> 
> For this particular patch, I would still like to see a core library
> provide the needed functionality. I just sent out an RFC of a possible
> implementation.
> 
> Regardless, a key point is that this isn't about "big-endian", it is
> about endianness opposite to the executing processor.

I commented on just this aspect under your RFC. I think I disagree, for
two reasons:

- As long as the specs are LE-only, "endianness opposite to the
executing processor" is needless complication / speculative generality
in my eyes.

- Even if we supported multiple endiannesses on the CPU front, the API
names should reflect the *device* byte order, not the CPU byte order.
Think of the case when the same platform device is integrated on board
B1 whose CPU is LE, and on board B2 whose CPU is BE. If we name the APIs
after the CPU byte order, then the same driver source code will be
misleading on one of the boards. Whereas, if we name the APIs after
device byte order, then the driver source code will be correct
regardless of board / CPU, and only the internal workings of the APIs
should change. For example, on a BE CPU / platform, the "normal" (LE)
IoLib class should be resolved to an instance that byte-swaps
internally, and the BE IoLib class should be resolved to an instance
that is transparent internally.

Thanks
Laszlo
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