As a preparation for adding the ICU (Interrupt Consolidation Unit) library implementation a correct CP110 count is required. Do it for Armada70x0Db and fix depending XHCI/AHCI PCD's accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <[email protected]> Reviewed-by: Ard Biesheuvel <[email protected]> --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc index 5ccee1b..2240a57 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -53,6 +53,9 @@ # ################################################################################ [PcdsFixedAtBuild.common] + #CP110 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|2 @@ -129,8 +132,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } #RTC -- 2.7.4 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
