On 1/7/2019 9:05 AM, Eric Dong wrote:
Enhance debug message format to let them easy to read.

Cc: Ruiyu Ni <ruiyu...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.d...@intel.com>
---
  .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c      | 17 +++++++++++------
  1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c 
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 0a74d448c8..624ddee055 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -473,8 +473,9 @@ DumpRegisterTableOnProcessor (
      case Msr:
        DEBUG ((
          DebugPrintErrorLevel,
-        "Processor: %d:   MSR: %x, Bit Start: %d, Bit Length: %d, Value: 
%lx\r\n",
+        "Processor: %04d: Index %04d, MSR  : %08x, Bit Start: %02d, Bit Length: 
%02d, Value: %016lx\r\n",
          ProcessorNumber,
+        FeatureIndex,
          RegisterTableEntry->Index,
          RegisterTableEntry->ValidBitStart,
          RegisterTableEntry->ValidBitLength,
@@ -484,8 +485,9 @@ DumpRegisterTableOnProcessor (
      case ControlRegister:
        DEBUG ((
          DebugPrintErrorLevel,
-        "Processor: %d:    CR: %x, Bit Start: %d, Bit Length: %d, Value: 
%lx\r\n",
+        "Processor: %04d: Index %04d, CR   : %08x, Bit Start: %02d, Bit Length: 
%02d, Value: %016lx\r\n",
          ProcessorNumber,
+        FeatureIndex,
          RegisterTableEntry->Index,
          RegisterTableEntry->ValidBitStart,
          RegisterTableEntry->ValidBitLength,
@@ -495,8 +497,9 @@ DumpRegisterTableOnProcessor (
      case MemoryMapped:
        DEBUG ((
          DebugPrintErrorLevel,
-        "Processor: %d:  MMIO: %lx, Bit Start: %d, Bit Length: %d, Value: 
%lx\r\n",
+        "Processor: %04d: Index %04d, MMIO : %08lx, Bit Start: %02d, Bit Length: 
%02d, Value: %016lx\r\n",
          ProcessorNumber,
+        FeatureIndex,
          RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 
32),
          RegisterTableEntry->ValidBitStart,
          RegisterTableEntry->ValidBitLength,
@@ -506,8 +509,9 @@ DumpRegisterTableOnProcessor (
      case CacheControl:
        DEBUG ((
          DebugPrintErrorLevel,
-        "Processor: %d: CACHE: %x, Bit Start: %d, Bit Length: %d, Value: 
%lx\r\n",
+        "Processor: %04d: Index %04d, CACHE: %08lx, Bit Start: %02d, Bit Length: 
%02d, Value: %016lx\r\n",
          ProcessorNumber,
+        FeatureIndex,
          RegisterTableEntry->Index,
          RegisterTableEntry->ValidBitStart,
          RegisterTableEntry->ValidBitLength,
@@ -517,8 +521,9 @@ DumpRegisterTableOnProcessor (
      case Semaphore:
        DEBUG ((
          DebugPrintErrorLevel,
-        "Processor: %d: Semaphore: Scope Value: %s\r\n",
+        "Processor: %04d: Index %04d, SEMAP: %s\r\n",
          ProcessorNumber,
+        FeatureIndex,
          mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, 
InvalidDepType)]
          ));
        break;
@@ -833,7 +838,7 @@ ProgramProcessorRegister (
                ApLocation->Thread;
        DEBUG ((
          DEBUG_INFO,
-        "Processor = %lu, Entry Index %lu, Type = %s!\n",
+        "Processor = %08lu, Index %08lu, Type = %s!\n",
          (UINT64)ThreadIndex,
          (UINT64)Index,
          mRegisterTypeStr[MIN 
((REGISTER_TYPE)RegisterTableEntry->RegisterType, InvalidReg)]

Reviewed-by: Ray Ni <ray...@intel.com>

--
Thanks,
Ray
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