On Sun, 2013-01-20 at 20:36 -0600, David Woodhouse wrote:
> Here's a slightly more concrete version of that proposal:

The implementation may look something like this:

diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c 
b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c
index dfdac35..fe79064 100644
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c
@@ -1184,6 +1184,22 @@ GenericLegacyBoot (
                            0x40000,
                            &Granularity
                            );
+  if (Private->Legacy16Table->TableLength >= 
OFFSET_OF(EFI_COMPATIBILITY16_TABLE, UmbEnd) &&
+      Private->Legacy16Table->UmbStart != 0 && Private->Legacy16Table->UmbEnd 
!= 0) {
+
+    // Here we could reduce UmbStart down as far as Private->OptionRom, taking 
into
+    // account the granularity of the access control.
+
+    DEBUG((EFI_D_INFO, "Unlocking UMB RAM region %x-%x\n",
+      Private->Legacy16Table->UmbStart << 12, Private->Legacy16Table->UmbEnd 
<< 12));
+
+    Private->LegacyRegion->UnLock (
+                             Private->LegacyRegion,
+                             Private->Legacy16Table->UmbStart << 12,
+                             (Private->Legacy16Table->UmbEnd - 
Private->Legacy16Table->UmbStart) << 12,
+                             &Granularity
+                             );
+  }
   //
   // Lock attributes of the Legacy Region if chipset supports
   //
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c 
b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c
index 910ed41..94852de 100644
--- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c
+++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c
@@ -2269,6 +2269,7 @@ LegacyBiosInstallRom (
   UINT32                LocalTime;
   UINT32                StartBbsIndex;
   UINT32                EndBbsIndex;
+  UINT32                MaxRomAddr;
   UINTN                 TempData;
   UINTN                 InitAddress;
   UINTN                 RuntimeAddress;
@@ -2284,7 +2285,13 @@ LegacyBiosInstallRom (
   Function        = 0;
   VideoMode       = 0;
   PhysicalAddress = 0;
+  MaxRomAddr      = PcdGet32 (PcdEndOpromShadowAddress);
 
+  if (Private->Legacy16Table->TableLength >= 
OFFSET_OF(EFI_COMPATIBILITY16_TABLE, UmbEnd) &&
+      Private->Legacy16Table->UmbStart != 0 && Private->Legacy16Table->UmbEnd 
!= 0 &&
+      MaxRomAddr > (Private->Legacy16Table->UmbStart << 12)) {
+     MaxRomAddr = Private->Legacy16Table->UmbStart << 12;
+  }
   PciProgramAllInterruptLineRegisters (Private);
 
   if ((OpromRevision >= 3) && (Private->Csm16PciInterfaceVersion >= 0x0300)) {
@@ -2316,7 +2323,7 @@ LegacyBiosInstallRom (
     //   then test if there is enough space for its RT code
     //
     RuntimeAddress = Private->OptionRom;
-    if (RuntimeAddress + *RuntimeImageLength > PcdGet32 
(PcdEndOpromShadowAddress)) {
+    if (RuntimeAddress + *RuntimeImageLength > MaxRomAddr) {
       DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): 
EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
       gBS->FreePages (PhysicalAddress, EFI_SIZE_TO_PAGES (ImageSize));
       //
@@ -2334,7 +2341,7 @@ LegacyBiosInstallRom (
     //   test if there is enough space for its INIT code
     //
     InitAddress    = PCI_START_ADDRESS (Private->OptionRom);
-    if (InitAddress + ImageSize > PcdGet32 (PcdEndOpromShadowAddress)) {
+    if (InitAddress + ImageSize > MaxRomAddr) {
       DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): 
EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
       //
       // Report Status Code to indicate that there is no enough space for OpROM
diff --git a/IntelFrameworkPkg/Include/Protocol/LegacyBios.h 
b/IntelFrameworkPkg/Include/Protocol/LegacyBios.h
index 88f5980..e22b661 100644
--- a/IntelFrameworkPkg/Include/Protocol/LegacyBios.h
+++ b/IntelFrameworkPkg/Include/Protocol/LegacyBios.h
@@ -228,6 +228,16 @@ typedef struct {
   /// Maximum PCI bus number assigned.
   ///
   UINT8                             LastPciBus;
+
+  ///
+  /// Start address of UMB RAM (>> 24)
+  ///
+  UINT8                             UmbStart;
+
+  ///
+  /// End address of UMB RAM (>> 24)
+  ///
+  UINT8                             UmbEnd;
 } EFI_COMPATIBILITY16_TABLE;
 
 ///


-- 
dwmw2

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