Satish,
If BAR 0 is a 64-bit MMIO BAR, then the 64-bit request should work. However,
you do need to make sure that the value of the parameter 'x' is 64-bit aligned.
The EDK II PCI Bus Driver does have a PCD FeatureFlag that enables support for
unaligned Offset parameters (in your example the Offset parameter called 'x').
If the requested Offset is not aligned, then the request is converted to a
series of 8-bit transfers. If you are testing on a set of platforms where this
feature is enabled on some and disabled on others, it could explain the
behavior difference you are seeing.
//
// If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
}
}
A UEFI Driver for a PCI Controller should always guarantee that the Offset
parameter is aligned correctly to be conformant with the UEFI Spec and maximize
platform compatibility.
Best regards,
Mike
-----Original Message-----
From: Laszlo Ersek [mailto:ler...@redhat.com]
Sent: Tuesday, February 26, 2013 9:11 AM
To: edk2-devel@lists.sourceforge.net
Subject: Re: [edk2] Dell R720 server
On 02/26/13 06:22, satish kondapalli wrote:
> Hi,
>
> I developed option ROM Driver for my PCIe device. Driver is working fine
> on Intel servers. But on Dell R720 server, I am not able to access my
> BAR registers but i am able to access device config space.
>
> In Driver supported function, verified the Device ID,Vendor ID and
> returned EFI_SUCCESS. In my start function I enabled my pcie device with
> following API.
>
> Status = PciIo->Attributes(
> PciIo,
> EfiPciIoAttributeOperationEnable,
> EFI_PCI_DEVICE_ENABLE,
> NULL
> );
> After enabling my device, i accessed one register(at x offset) in my bar
> space with following API.
>
> Status = PciIo->Mem.Read(
> PciIo,
> EfiPciIoWidthUint64,
> 0,
> x,
> 1,
> &TmpAddr);
> if(EFI_ERROR(Status)) {
> Print(L"BAR READ Failed: status:%d\n",Status);
> }
>
> Above API giving error with status value as 2. But same code is working
> fine in Intel servers.
Try two 32-bit reads instead.
13.4 EFI PCI I/O Protocol
EFI_PCI_IO_PROTOCOL.Mem.Read()
[...] The caller is responsible for any alignment and I/O width
issues which the bus, device, platform, or type of I/O might
require. For example on some platforms, width requests of
EfiPciIoWidthUint64 do not work.
Laszlo
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