Thanks Girish, I have changed a bit your patch but it has been committed in
SVN rev14606.

BIT0 controls the Secure state (transition from Secure to Non-Secure world).
So it can be any of the Non-Secure state: EL2, EL1, EL0.

Replacing 'mov' by 'orr' instructions was the right fix. We start by doing a
load ('ldr') and then we add the EnableGrp0 and EnableGrp1 bits to the
original value.

> -----Original Message-----
> From: Girish K S [mailto:[email protected]]
> Sent: 26 August 2013 05:27
> To: [email protected]
> Cc: Olivier Martin
> Subject: [edk2] AArch64: ArmVExpressPkg: Remove dummy load instr
> 
> SCR_EL3 is the control register for setting exception level2
> modified the comment which can mislead.
> 
> The "ldr r0, [r1]" is overrided with a immediate "mov ro, #3"
> instruction. This mov instruction will over write the contents
> of the ro register. So remove the ldr instruction if intension
> is to mov #3. Or if previous value has to be retained then ORR
> can be used.
> 
> This patch assumes mov is the right instruction to be retained
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Girish K S <[email protected]>
> ---
>  .../Scripts/uefi-aarch64-bootstrap/boot.S          |    3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-
> bootstrap/boot.S b/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-
> bootstrap/boot.S
> index 24d5bb0..031f372 100644
> --- a/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-
> bootstrap/boot.S
> +++ b/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-
> bootstrap/boot.S
> @@ -57,7 +57,7 @@ _start:
>       b.ne    start_ns                        // skip EL3 initialisation
> 
>       mov     x0, #0x30                       // RES1
> -     orr     x0, x0, #(1 << 0)               // Non-secure EL1
> +     orr     x0, x0, #(1 << 0)               // Non-secure EL2
>       orr     x0, x0, #(1 << 8)               // HVC enable
>       orr     x0, x0, #(1 << 10)              // 64-bit EL2
>       msr     scr_el3, x0
> @@ -87,7 +87,6 @@ _start:
>       str     w0, [x1], #4
> 
>  2:   ldr     x1, =GIC_CPU_BASE               // GICC_CTLR
> -     ldr     w0, [x1]
>       mov     w0, #3                          // EnableGrp0 | EnableGrp1
>       str     w0, [x1]
> 
> --
> 1.7.9.5
> 





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