On Mon, Sep 23, 2013 at 4:17 AM, Olivier Martin <olivier.mar...@arm.com> wrote:
Still no main commit message...
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Olivier Martin <olivier.mar...@arm.com>
> ---
> diff --git a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.c
> b/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.c
> new file mode 100644
> index 0000000..c0480da
> --- /dev/null
> +++ b/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.c
> +EFI_STATUS
> +EFIAPI
> +VirtioPciIoRead (
> + IN VIRTIO_PCI_DEVICE *Dev,
> + IN UINTN FieldOffset,
> + IN UINTN FieldSize,
> + IN UINTN BufferSize,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN Count;
> + EFI_PCI_IO_PROTOCOL_WIDTH Width;
> + EFI_PCI_IO_PROTOCOL *PciIo;
> +
> + ASSERT (FieldSize == BufferSize);
> +
> + PciIo = Dev->PciIo;
> +
> + Count = 1;
> + switch (FieldSize) {
> + case 1:
> + Width = EfiPciIoWidthUint8;
> + break;
> +
> + case 2:
> + Width = EfiPciIoWidthUint16;
> + break;
> +
> + case 8:
> + // The 64bit PCI I/O is broken down into two 32bit reads to prevent
> + // any alignment or width issues.
> + // The UEFI spec says under EFI_PCI_IO_PROTOCOL.Io.Write():
> + //
> + // The I/O operations are carried out exactly as requested. The caller
> + // is responsible for any alignment and I/O width issues which the
> + // bus, device, platform, or type of I/O might require. For example on
> + // some platforms, width requests of EfiPciIoWidthUint64 do not work*/
> + Count = 2;
> + // fall through
It sounds like there is a preference to not use the standard UEFI
alignment restrictions here? (I guess this is okay for virt-io based
on the comment.)
If so, it seems like this routine is not adequate. For example, what
about 16 & 32-bit alignment restrictions?
-Jordan
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